Presentation slides for the ISTFA 2024 Tutorial session “Correlative Microscopy: In-Situ AFM-in-SEM Introduction, Capabilities, and Case Studies Semiconductor Materials and Batteries.”

Presentation slides for the ISTFA 2024 Tutorial session “Advanced FIB/SEM Sample Preparation and Analysis Techniques (2024 Update).”

Presentation slides for the ISTFA 2024 Tutorial session “Basics and Current Aspects of Scanning Electron Microscopy.”

Presentation slides for the ISTFA 2024 Tutorial session “Transmission Electron Imaging AND Diffraction in an SEM (aka, STEM-in-SEM): What, Why, and How To Do This in Your Microscope.”

We introduce a novel piece of hardware that allows researchers to extend a nanomanipulator needle further into the vacuum chamber of a dual beam FIB SEM without venting the system. This hardware innovation will elevate throughput and diminish the instrument's downtime, which is pivotal for transmission electron microscope (TEM) sample preparation—a process integral to semiconductor manufacturers where the demand for TEM samples is high due to their necessity for process characterization and failure analysis of integrated circuits. Traditionally, the manipulator needle shortens with each sample preparation, ultimately reaching a mechanical limit that necessitates system venting to install a new needle. This hardware innovation allows users to feed out more needle length into the vacuum chamber by twisting a knob on the outside of the FIB SEM.

Advanced semiconductor devices are disrupting traditional failure analysis workflows and creating demand for instrumentation that enables flexible capabilities to address these technology inflections. Such trends can be observed across multiple development areas, including faster processing, increased memory bandwidth, and power delivery. In every case, shrinking structures, complex packaging architecture, and advanced materials drive the need for efficient, precise targeting for regions of interest (ROI) over a wide range of length scales. An important example is the implementation of wide-bandgap (WBG) semiconductors, such as SiC and GaN, in advanced power devices. Various complexities are introduced, not only in device architecture, but also in defectivity analysis by conventional methods. As a result, high quality and high throughput failure analysis is achieved with specialized use of several plasma focused ion beam (PFIB) species best suited to these materials. Here we demonstrate such sample preparation for workflows involving electrical failure analysis (EFA) and localization, cross-sectional and volume analysis using scanning electron microscopy (SEM), as well as lamella preparation for transmission electron microscopy for physical failure analysis (PFA).

Soft defects—failures that manifest only under specific voltage, temperature, or frequency conditions—require specialized fault isolation techniques for accurate characterization. This paper demonstrates thermal response failure localization using scanning electron microscope (SEM) nanoprobing with an integrated thermal stage. While nanoprobing typically serves as the final step in fault isolation failure analysis (FIFA), thermal nanoprobing is essential for characterizing temperature-dependent parametric defects by enabling measurements at both passing and failing temperatures. We present three case studies: a "worse at cold" failure reproduction, a parametric root cause identification through thermal characterization, and a complex thermal failure that was uniquely isolatable through thermal nanoprobing. These cases illustrate the technique's effectiveness in analyzing temperature-dependent defects that occur outside room temperature conditions.

We demonstrate the effectiveness of combining top-down and cross-sectional electron beam induced current (EBIC) imaging with SEM nanoprobe analysis to identify subtle front-end defects in advanced FinFET technology. Our approach successfully localized a novel fin nanocrack defect that had previously eluded detection through conventional TEM imaging. This systematic resistive pMOS failure, observable only in memory arrays at 150°C, exemplifies the power of EBIC as an alternative to scanning capacitance microscopy for detecting dopant anomalies and subtle defects. The sample preparation and EBIC methodologies presented here are broadly applicable across CMOS technologies, offering a versatile approach to defect analysis.

This work employs an easy-to-use method to quickly find and characterize leakage currents on a semiconductor sample by combining electrical fault isolation and electrical measurements. By using a simple add-on for a probing system’s tip holders, a prober is transformed into a scanning device that measures currents through a sample’s surface and visualizes the currents in a 2D color map that can be superimposed onto the SE image. As a case study, an area of 1.5 µm x 1.5 µm of a 3 nm device was scanned while the current through the contacts was measured and visualized with Current Imaging (CI) and gate currents were characterized. One leaking gate could be identified and the position of the failure was localized using Electron Beam Induced Resistance CHange (EBIRCH) imaging. This technique also avoids any damage caused by electron beam irradiation as the beam can be switched off during scanning.

In semiconductor manufacturing, the process of laser dicing can result in a loss of yield due to defects associated to the laser interaction with the sample. These defects can be difficult to identify, especially before a proper tuning of the process. Traditional investigation methods, like infrared (IR) inspection and focused-ion beam scanning electron microscopy (FIB-SEM) analysis, are labor-intensive and lack comprehensive insights. Here, we propose a robust correlative microscopy (CM) workflow integrating IR, X-ray Microscopy (XRM), and FIB-SEM tomography analyses, leveraging artificial intelligence (AI) driven algorithm for time- and quality-improved dataset reconstruction, automatic segmentation and defect site identification. Our approach streamlines defect identification, preparation, and characterization. Through AI-enhanced methodologies, as well as femtosecond (fs) laser, we optimize investigation efficiency and extract crucial information about defects properties and evolution. Our research aims to advance semiconductor failure analysis by integrating AI for enhanced defect localization and high-quality 3D dataset acquisition in the realm of laser dicing processes.

Over the past decade, the semiconductor industry has increasingly focused on packaging innovations to improve device performance, power efficiency, and reduce manufacturing cost. The recent heterogeneous integration offers an attractive solution in advanced IC packaging because it enables the integration of diverse functional components, such as logic, memory, power modulator, sensor on a single package platform. However, the adoption of the emerging structures, materials and components in advanced packages has challenged the existing fault isolation and analysis techniques. One of the major challenges is the limited accessibility to defects because fault regions are often located deep within devices. Without high-accuracy positional information of a defect, physical cross-sectioning and FIB polishing may alter or destroy the evidence of root causes. A non-destructive microscopic approach is preferred to map defective sites and surrounding structures. However, this method is limited by spatial resolution, especially for analyzing novel submicron interconnects such as fine pitch microbumps, redistribution layers (RDLs), and hybrid bonds. In this paper, we report an AI powered correlative microscopic workflow, where non-destructive X-ray imaging, FIB polishing and high-resolution SEM analyzing techniques are combined to solve the accessibility problem. Because 3D X-ray imaging may take a larger fraction of the time span over the entire workflow, a deep-learning based reconstruction method was applied to accelerate data acquisition. Several next-generation packages, fan-out wafer-level package (FOWLP) and hybrid bonds with sub 10 µm pitch, were used as the test vehicles to demonstrate the workflow performance and efficiency.

An innovative method of characterizing p/n junctions and finding defects in SiC MOSFETs is discussed. First, a baseline technique is considered, which involves OBIRCH analysis of shorting paths after etching off the surface metal. The resolution, however, is not satisfactory. Top surface EBIC and EBIRCH results are then presented. Single-probe imaging with EBIC on gates with a 25 kV SEM (Scanning Electronic Microscopy) is shown to be able to image sub-surface depletion zones in the sample. Further measurements by EBIRCH isolated the precise spot of the defect.

Milling experiments were undertaken with an AFM-in-SEM system to examine various layers in the SRAMs of a 3 nm finFET node technology chip. The simultaneous Conductive AFM and tomographic milling operation provided feedback as to the exact state of delayering in the sample. Despite the relatively rough appearance of some areas of the chip, the milling by the AFM tip was able to create local areas with high planarity. The AFM measurement provided the exact moment certain structures were polished through. Discussion of various electrical modes in the analysis that might provide clearer indications of breakthrough is also undertaken in this paper.

This paper presents a root cause analysis case study of defective Hall-effect sensor devices. The study identified a complex failure mode caused by chip-package interaction, which has a similar signature to discharging defects such as ESDFOS. However, the study revealed that the defect was induced by local mechanical force applied to IC structures due to the presence of large irregular-shaped filler particles within the mold compound. Extensive failure analysis work was conducted to identify the failure mode, including the development of a new backside analysis strategy to preserve the mold compound during IC defect localization and screening. A combination of different failure analysis techniques was used, including CMP delayering, PFIB trenching, SEM PVC imaging, and large area FIB cross-sectioning. The study found that the mold compound of the package caused thermos-mechanical strain onto the silica filler particle due to epoxy shrinkage during the molding process. Additionally, extra-large, irregularly shaped filler particles (called twin particles), located on top of the chip surface, can cause locally high compression stresses onto the IC layers, initiating cracks in the isolation layers under certain conditions forming a leakage path over the time. Thermo-mechanical finite element analysis was applied to verify the mechanical load condition for these large irregular-shaped filler particles. As a result, an additional polyimide layer was introduced onto the IC to mitigate the mechanical stress of mold compound particles to avoid this failure mode.

It has been a challenge to perform failure analysis for miniaturization of process node technology in high-speed transceiver. Failure analysis plays an important role in root cause analysis to enable R&D, product quality & reliabily improvement. This paper demonstrated an effective FA approach on a real case with ADPLL functional failure within a high-Speed transceiver in complex sub-nano FPGA. This successful case is achieved by incorporating Analog Probe (APROBE), Infrared Emission Microscopy (IREM), extensive layout study, delayering, Nanoprobing and Scanning Electron Microscopy (SEM) for defect localization.

As technology nodes continue to shrink, Scanning Electron Microscopy (SEM) inspection and electrical characterization of transistors has increased in difficultly. This is particularly true with early back end-of-line (BEOL) features like metal and via layers which are traditionally imaged at 3-5 keV. At these layers, this energy is capable of beam contamination, introducing electrical complications particularly with transistor probing. This electrical data is necessary to characterize subtle defects at front end-of-line (FEOL). Thus, the implementation of beam deceleration for the inspection of these layers provides a useful combination of low landing energy and higher image quality. This technique proves to aid in preserving the ability to electrically characterize any defect at the subsequent layers beneath. This increases the quality of the Physical Failure Analysis (pFA) workflow when implemented at early BEOL layers by providing higher quality images as well as preserving the electrical properties of the transistors for subtle FEOL defect characterization.

Scanning Electron Microscope (SEM) is a valuable tool for measuring Critical Dimensions (CD) of semiconductor devices at the nanometer scale. Vertical SEM application is one of the applications for high accurate CD measurement on cross-sectional surface. Even a slight stage tilt angle change of the vertical sample can impact CD values in nanometer scales of the sample surface features. For accurate CD measurements, it is essential to ensure the sample is positioned correctly to acquire the sample image. However, it is challenging to achieve a perfect alignment with the incident beam direction and the accurate perpendicular direction on the cross-sectional surface on SEM tool. To achieve an ideal vertical positioning of the sample, the combination of the stage tilt axis and stage rotation axis can be used. Exact calculation is required to achieve an accurate CD measurement. In this paper, a calculation method of the tilt angle correction to achieve a perpendicular angle to the surface and its verification method are described. Reliable measurement can be achieved by employing an automated script for compensation. We also demonstrate an approach for highly reliable angle correction and improved metrology results in this paper.

Continued advancements in the architecture of 3D packaging have increased the challenges in fault isolation and failure analysis (FA), often requiring complex correlative workflows and multiple inference-based methods before targeted root cause analysis (RCA) can be performed. Furthermore, 3D package components such as through-silicon-vias (TSVs) and micro-bumps require sub-surface structural characterization and metrology to aid in process monitoring and development throughout fabrication and integration. Package road-mapping has also called for increased die stacking with decreased pitch, TSV size, and die thickness, and thus requires increased accuracy and precision of various stateof- the-art analytical techniques in the near future. Physical failure analysis (PFA), process monitoring, and process development will therefore depend on reliable, high-resolution data directly measured at the region of interest (ROI) to meet the complexity and scaling challenges. This paper explores the successful application of plasma-FIB (PFIB)/SEM techniques in 2D and 3D regimes and introduces diagonal serial sectioning at package scales as a novel approach for PFA and metrology. Both 2D and 3D analysis will be demonstrated in a high bandwidth memory (HBM) package case-study which can be applied more broadly in 3D packaging.

Focused-Ion Beam Scanning Electron Microscopy (FIB-SEM) tomography is a high resolution three-dimensional (3D) imaging method with applications in failure analysis and metrology of semiconductor devices. For the smallest logic and memory structures currently in use, it requires single-digit nanometer 3D resolution. In this resolution range, avoiding distortion artifacts in the data becomes crucial. We present examples and discuss ways to reduce the likelihood of such artifacts during the data acquisition, as well as how to mitigate them in post-processing, and therefore increase the data quality.

Insulated Gate Bipolar Transistors (IGBT) and silicon carbide (SiC) based MOSFETs have become the predominantly used power semiconductors in particular in automotive applications. For failure analysis of such devices, site-specific access to subsurface fault sites is required, as is understanding their construction and junction profiles, and how the device turns on. We have applied focused ion beam-scanning electron microscopy (FIB-SEM) tomography to visualize inner structure and dopant distributions of an IGBT and of a SiC MOSFET in three dimensions (3D). Such 3D data can be used to complement 2D electron beam induced current (EBIC) measurements obtained at site-specific FIB cross-sections in these devices.