In DRAM devices, many failures only appeared in a specific operating state on chips during functional tests. Dynamic photon emission microscopy (D-PEM) is a useful technique in failure analysis for emitted photons when the device under test (DUT) is electrically exercised. Therefore, D-PEM analysis combined with specific external triggers in functional test can activate the chip, and thereby expand the range of detectable defects and increase the chances of finding a specific failure mode. In this study, we will discuss various cases of external triggers applied from the tester. This method can be used to detect emission which did not show up in conventional test condition in PEM method for localizing active fails in DRAM. Then, after localizing the site of failure, more detailed physical visualization by Focused Ion Beam (FIB) cross section image, Transmission Electron Microscope (TEM), and Energy Dispersive X-ray microscopy (EDX) revealed main causes of failure. We believe that our method could be a future solution for increasingly difficult and diverse failures modes in the DRAM industry.

Time-resolved emission microscopy (TREM) enables non-intrusive failure analysis of integrated circuits through photoemission detection at picosecond resolution. While photoemission occurs in both functional and faulty ICs, certain emission patterns distinctively indicate device defects. The primary mechanism driving this phenomenon is hot carrier luminescence in silicon, where carriers with excess kinetic energy release photons through intraband transitions. In CMOS logic, these emissions occur when MOSFETs switch between logical states, generating drain-to-source current flow. However, modern large-scale ICs present unique challenges for photoemission analysis: their lower operating voltages and reduced switching currents result in fewer photon emissions, predominantly in the infrared spectrum. We address these limitations by implementing superconducting-nanowire single-photon detectors (SNSPDs), enabling high-sensitivity photoemission microscopy for advanced IC failure analysis.

Secure edge devices and the need for hardware security are of paramount importance due to the growing demand for cybersecurity. Hardware security has been strengthened using complex architecture to provide uncompromisable security and prevent malicious cybersecurity attacks. To prevent unauthorized access using even the most advanced failure analysis (FA) techniques, the Hardware Security Module (HSM) implements cryptographic algorithms and data obfuscation using many raw combinational logic and state machines. When a newly taped-out device fails to operate or fails to come out of its secure boot-up sequence, how can we know whether a defect is present or if the security block reacted to a design error? This paper discusses various real-world examples of FA challenges related to first silicon debug, including secure IP. We explore the unique approaches required to make sense of collected Laser Voltage Probe (LVP), Photon Emission Microscopy (PEM), and Laser Logic State Mapping (LLSM) data. We discuss some of the most advanced FA techniques' strengths and weaknesses and illustrate how system architecture related to securing data can be modified to alter the effectiveness of each. We explain in detail why specific FA techniques can be defeated by built-in security and where FA techniques can be enabled by clever triggering schemes or looping on areas of code while looking for specific behaviors. This paper also talks about the limitations of analyzing complex architecture being good from a security point of view. We conclude by summarizing the threat FA tools present to secure IP and comment on steps that could be taken to further protect internal state machines and sensitive logic areas from even the most well-equipped FA labs. Thus, this work gives an introspective thought as to how Optical Fault Isolation (OFI) techniques could be perceived as a threat to various security applications and points to trade-offs between the ability to analyze versus hardware security.

Hard failures, especially the Stuck at Reset failures insensitive to voltage, frequency, and temperature, are among the toughest to debug using the conventional Electrical Fault Isolation Methodology. These types of failures have no test data and no diagnostic information. Because of the failure being stuck at the reset sequence and being a hard failure, methodologies like Laser-Assisted Device Alteration (LADA) cannot be carried out. Photon Emission Microscopy (PEM) may exhibit numerous differences for good vs. bad die, however, most emission signatures typically indicate where IP is stuck in reset but do not indicate the actual root cause. Laser Voltage Probe (LVP) is the most logical way to proceed, but since Power-on Reset (POR) signals typically transition only once per test in conjunction with hard power cycling, the LVP averaging became very difficult as the hard power cycling increased the time of the loop drastically. This paper discusses a novel methodology of modulating power supply voltages within a looping pattern to optically probe the critical internal POR signal transitions effectively and debug the power sequencing of the device. This method is carried out through a custom test setup where a particular power supply of interest is modulated within the test loop without powering down other supplies connected, thereby avoiding the time penalty required for complete power down and power up. The method also synchronizes internal signals associated with POR to a tester-generated trigger in order to successfully obtain recognizable internally extracted POR-associated waveforms. This methodology is conveyed by explaining a complex functional failure analysis case study while highlighting where conventional failure analysis methods could not be used directly to identify the root cause of failure. This paper also describes another case study to explain how parametric information, such as the current profile using the current probe obtained during the test on a pass vs. fail device, can provide valuable information and help debug stuck-in reset failures.

Photon Emission Microscopy (PEM) is a popular technique for microelectronics failure analysis by detecting the photon emission from a defective circuit, when a failing device is electrically exercised at certain voltage. The photon emission contains physical location information, photon emission spectral information and photon emission intensity information. People often use the physical location information to localize a defective circuit and guide the follow-up physical failure analysis to find the defects. However, this procedure does not always work. Sometimes, it shows no defect found (NDF). In this paper, we propose a new computer vision-based analysis of the photon emission intensity for identifying the root cause of the excessively high IDDQ at elevated Vdds. The procedure includes collecting photon emissions at different Vdds and a follow-up photon emission intensity analysis with computer vision techniques. The procedure was applied on a case of microprocessor chip. After analyzing the dependencies of photon emission intensity on Vdd for 4 types of circuits, it was concluded that the SRAM circuit leakage is the root cause of the excessively high IDDQ at elevated Vdd.

We present the first experimental demonstration of on demand bit-level Static Random Access Memory (SRAM) validation and isolation through the exploitation of a continuous wave (CW) 785nm Laser-Induced Fault Analysis (LIFA) system. Through careful test pattern edits and the observation of a simple pass/fail flag, the ability to spatially map the physical location of pre-selected bits in 40nm, 16nm, and 5nm SRAM arrays using correlation units is confirmed. This work demonstrates a novel and highly-efficient methodology for rapid bit-level logical-to-physical identification. It also improves localization efficacy over conventional bitmap validation best-known methods (BKM) which typically rely on post-fail Photo-Emission Microscopy (PEM) and/or Soft Defect Localization / Laser-Assisted Device Alteration (LADA) performed on an actual fail unit. This new technique re-defines the state-of-the-art in SRAM bitmap validation and localization and offers a pathway to significantly improve cycle time for both product bitmap qualification and subsequent root cause identification.

High-speed time-resolved emission analysis is an attractive failure analysis technique because of its non-invasiveness. Super-conductive nanowire single photon detector (SNSPD or SSPD) is a key candidate of key device for time-resolved emission analysis. In this paper, we demonstrate time-resolved emission and its application of spatial resolution enhancement. We could confirm that time-resolved emission imaging can enhance spatial resolution by simple mathematical operations compared to static emission analysis, which is effective for finding emission spots before detailed time-resolved data investigations.

Computer Aided Design (CAD) alignment is a key requirement for dynamic fault isolation. CAD alignment between the drawn layout and the physical reflected image from the device helps to navigate and observe the physical location of the suspected circuitry. Conventionally, large structures such as the boundaries of Static Random-Access Memory (SRAM) cells are used as reference for coarse CAD alignment and the shallow trench isolation (STI) layer is used for fine alignment while analyzing logic cell structures. With technology scaling, especially into FinFETs, the fine alignment has become more challenging as the reflected optical image of STI layer is poorly resolved. In this paper, we discuss the enhanced CAD alignment techniques in Synopsys Avalon that uses features “Minimum object size (dimension based)”, and “net search” developed in the CAD tool, Synopsys Avalon, combined with Amplitude lock-in Dynamic Photon Emission Microscopy (D-PEM) technique to assist a finer CAD alignment.

Near Infra-Red (NIR) techniques such as Laser Voltage Probing/Imaging (LVP/I), Dynamic Laser Stimulation (DLS), and Photon Emission Microscopy (PEM) are indispensable for Electrical Fault Isolation/Electrical Failure Analysis (EFI/EFA) of silicon Integrated Circuit (IC) devices. However, upcoming IC architectures based on Buried Power Rails (BPR) with Backside Power Delivery (BPD) networks will greatly reduce the usefulness of these techniques due to the presence of NIR-opaque layers that block access to the transistor active layer. Alternative techniques capable of penetrating these opaque layers are therefore of great interest. Recent developments in intense, focused X-ray microbeams for micro X-Ray Fluorescence (μXRF) microscopy open the possibility to using X-rays for targeted and intentional device alteration. In this paper, we will present results from our preliminary investigations into X-ray Device Alteration (XDA) of flip-chip packaged FinFET devices and discuss some implications of our findings for EFI/EFA.

Photon Emission Microscopy (PEM) analysis is one of the most common used FA techniques to identify the root cause of failures within ATPG scan logic due to its ease of setup and less invasive nature. While conducting photon emissions, the device is made to operate in the fail mode by running a production test vector to look for anomalous emissions or hot spots that could narrow down the area of interest (AOI) for subsequent Physical Failure Analysis (PFA). However, if there is no clue from emission analysis in the case of a hard failure with no sensitivity to voltage, frequency, or temperature, FA debug will be challenging. This paper shows how PEM analysis success may be further improved through logic state circuit study using a DFT ATPG diagnostic platform. Logic state truth table and its relative test pattern will be built based on the diagnostic data using in-house scripts, and the test program can then be changed to the required condition of the circuitry. With the altered logic state, new emission data can be collected, which could potentially reveal new clues to the investigation.

This presentation provides an overview of photonic measurement techniques and their use in isolating faults and locating defects in ICs. It covers transmission, reflectance, and absorption methods, describing key interactions and important parameters and equations. Reflectance methods discussed include electro-optical probing (EOP), electro-optical frequency modulation (EOFM), and laser-voltage imaging (LVI). Absorption methods covered include those based on the absorption of light in semiconductors, as in optical beam induced current (OBIC), light-induced voltage alteration (LIVA), and laser-assisted device alteration (LADA), and those based on absorption in metals, as in thermally induced voltage alteration (TIVA), optical beam induced resistance change (OBIRCH), and thermoelectric voltage generation or Seebeck effect imaging (SEI). The presentation also covers thermoluminescence (lock-in thermography) and electroluminescence (photon emission) measurement methods and assesses hardware security risks posed by current and emerging photonic localization techniques.

This presentation is a pictorial guide to the selection and application of measurement methods for defect localization. The presentation covers passive voltage contrast (PVC), nanoprobing, conductive atomic force microscopy, and photon emission microscopy (PEM). It describes signal types, how the measurements are made, the sensing mechanisms involved, and the output that can be expected.

In this paper, we discuss the use of spontaneous photon emission microscopy (PEM) for observing filaments formed in HfO 2 resistive random access memory (ReRAM) cells. The setup employs a CCD and an InGaAs camera, revealing photon emissions in both forward ( set ) and reverse ( reset ) bias conditions. Photon emission intensity is modeled using an electric-field equation and inter-filament distance and density are determined assuming a uniform spatial distribution. The paper also discusses the use of high frame rate and prolonged photon emission measurements to assess lifetime and reliability and explains how single filament fluctuations and multiple filaments in a single cell were observed for the first time.

This paper describes a procedure for preparing packaged GaN devices for photon emission microscopy from the backside, which has proven to be an effective method for isolating faults. The deprocessing technique was developed for GaN devices formed on thick p ++ silicon substrates mounted in quad-flat no-lead (QFN) packages connected by gold wires. It consists of mechanical polishing, which removes backside metal and packaging material, and selective etching, which quickly etches the silicon while leaving the gold wires intact for electrical measurements. The authors describe each step of the process in detail and explain how emission spots are marked with a UV laser and analyzed in a FIB-SEM system to determine the underlying cause of failure.

Vertical-cavity surface-emitting lasers (VCSELs) have many advantages over edge-emitting devices, but they tend to be more sensitive to increasing current density both in lifetime and reliability. To better understand this relationship, the authors investigated the cause of 35 failures involving GaAs-based oxide-confined VCSELs. This paper presents a summary of the procedures, methods, and equipment used, the defects and damages observed, and the root causes behind each failure. The authors followed a standard failure analysis workflow consisting of PEM and OBIRCH fault isolation, plan view TEM to confirm the location and distribution of defects, and cross-sectional TEM (XTEM) to determine the profile of a defect at a specific site. All failures examined could be attributed to one of four basic failure mechanisms: burnout due to ESD, dislocations, oxide diffusion, and oxide delamination.

Defects associated with metal-insulator-metal (MIM) capacitor failures can be difficult to locate using conventional fault isolation techniques because the capacitors are usually buried within a stack of back-end metal layers. In this paper, the authors explain, step by step, how they determined the cause of MIM capacitor failures, in one case, in an overvoltage protection device, and in another, a high-speed digital isolator circuit. The process begins with a preliminary fault isolation study based on OBIRCH or PEM imaging followed by more detailed analyses involving focused ion beam (FIB) cross-sectioning and delayering, micro- or nano-probing, resistive or voltage contrast imaging, and other such techniques.

This paper presents an alternative approach for analyzing complex scan chain failures in which there are multiple candidates that could be the root cause. It demonstrates the approach on an automotive IC with several failing flip-flops. An analysis of the interconnections shared by the failing devices reveals a common clock branch where the root cause is likely to reside. Photo-emission microscopy (PEM) is then used to verify the existence of a defect which, based on passive voltage contrast, is determined to be an open path.

This paper explains how tunneling atomic force microscopy (AFM) was used to determine the cause of leakage in FinFETs along the boundary of SRAM cells. The leaking devices were electrically isolated using photoemission microscopy, but conventional FA techniques, including SEM and TEM imaging, found no structural abnormalities. Suspecting that the failures may be due to dopant-related issues, the authors obtained cross sections of both good and bad devices and scanned them in a tunneling AFM. The paper describes the sample preparation process and includes cross-sectional images showing the difference between good and bad transistors. In SRAM areas where no leakage occurred, the fins are well defined and evenly spaced. However, in the area where an emission spot was observed, two of the fins appear to be overlapping, the result of n-well implants that merged.

For unique single failures, which tend to be the case in customer return and reliability failures, selecting another sample or performing root cause deconvolution is not an option, and if diagnostic tests are not conclusive, it becomes necessary to extend the effectiveness of automatic test pattern generator (ATPG) diagnosis in order to determine the failure mechanism. This paper proposes a way to improve resolution using single-shot logic and high-resolution targeted patterns. Two cases are presented to demonstrate the approach and show how it performed on actual failing units.

This paper describes optical and electron beam based fault isolation approaches for short and open defects in nanometer-scale through-silicon via (TSV) interconnects. Short defects are localized by photon emission microscopy (PEM) and optical beam-induced current (OBIC) techniques, and open defects are isolated by active voltage contrast imaging in a scanning electron microscope (SEM). The results are confirmed by transmission electron microscopy (TEM) cross-sectioning.