Abstract There are several variants of artificial intelligence (AI) hardware structures that are under study by the semiconductor industry for potential use in complementary metal–oxide–semiconductor (CMOS) designs. This paper discusses some of the failure analysis challenges that have appeared in discrete test structures and test arrays developed as part of an exploratory phase-change memory (PCM) program at IBM's Albany AI Hardware Research Center.

Abstract This paper presents the results of an investigation to gain a better understanding of the impact of wafer substrate copper (Cu) contamination on FinFET devices. A chip from a wafer free of Cu contamination and several chips near a Cu contaminated wafer edge were sampled for chemical, structural, and morphological analysis and electrical device performance testing. The contaminated wafer was also annealed at high temperature, trying to drive Cu diffusion further into the Si substrate. TEM analysis revealed that the Cu interacted with Si to form a stable η-Cu 3 Si intermetallic compound. SIMS analysis from the backside of the wafer detected no Cu even after most of the backside material was removed. Likewise, electrical nanoprobing showed no parametric drift in the FinFETs near the edge of the wafer, comparable to device behavior in a Cu-free Si substrate. These results indicate that the formation of η-Cu 3 Si with a well-defined crystalline structure and stable stoichiometry immobilizes Cu diffusion in the Si substrate. In other words, the impact of Cu diffusion in silicon has no effect on device performance as long as η-Cu 3 Si does not form in the FinFET channel or short any structures within the chip.

Abstract This paper provides an overview of the semiconductor analysis process at BMW. It explains how it was developed and how it differs from the failure analysis process used in semiconductor fabs. It describes the general process flow from first analyses through descending levels of localization at different length scales. It discusses sample preparation procedures, test methods and equipment, and advanced techniques. In the work presented here, the authors explain how they combined ToF-SIMS with STEM lamella preparation in a FIB-SEM, which allowed them to correlate concentration variances in an underlying layer with surface anomalies discovered during light microscope inspection.

Abstract Analog components are still an important aspect of our society's electronic portfolio. They play a role in the emerging and expanding 5G electronic industry, for instance. NPN bipolar junction transistors (BJTs) are the foundation of many analog circuits and have continually evolved to meet more demanding specifications. Certain embodiments of these NPNs, however, pose difficulties in failure analysis. Vertical NPN BJTs, with nanometer thick junctions extending several microns in length, are one such example. Although the high aspect ratio dimensions of these devices provide desired performance improvements, a subtle nanometer-scale defect anywhere along their length can cause electrical shifts detrimental to analog circuits. This paper examines the nature of these defects and explains how to isolate them using common failure analysis tools and special techniques.

Abstract In this paper, we discuss the use of spontaneous photon emission microscopy (PEM) for observing filaments formed in HfO 2 resistive random access memory (ReRAM) cells. The setup employs a CCD and an InGaAs camera, revealing photon emissions in both forward ( set ) and reverse ( reset ) bias conditions. Photon emission intensity is modeled using an electric-field equation and inter-filament distance and density are determined assuming a uniform spatial distribution. The paper also discusses the use of high frame rate and prolonged photon emission measurements to assess lifetime and reliability and explains how single filament fluctuations and multiple filaments in a single cell were observed for the first time.

Abstract This study shows that a high-volume TEM workflow can be achieved for inline defect characterization by adding a defect marking step using commercially available tools. A simple user-assisted defect marking procedure added to a conventional automated ex-situ lift-out TEM workflow increased throughput by a factor of nearly three and reduced man-hours by an order of magnitude, a significant improvement over conventional TEM workflows.

Abstract The automation of TEM imaging and lamella preparation using focused ion beam (FIB) technology has gained significant momentum, particularly in the development of microprocessors. A key requirement of automating TEM sample preparation is ensuring consistent thickness control and accurate targeting of features of interest in the ultra-thin lamella. This work examines the factors that impact both metrics. It explains how FIB pattern calibration requires milling to be divided into steps to minimize the effects of drift, how the height of the protective cap on the ion-beam tip influences sample thickness, and how FIB aperture erosion has little impact on lamella thickness until it reaches a certain point where the lamella profile cannot be reliably maintained. It was also found that the tail of the ion beam remains invariant during aperture degradation in the operable range and that it plays a prominent role in determining the cross-sectional thickness of the TEM lamella.

Abstract This paper describes an accurate and controllable delayering process to target defects in new materials and device structures. The workflow is a three-step process consisting of bulk device delayering by broad Ar ion beam milling, followed by plan view specimen preparation using a focused ion beam, then site-specific delayering via concentrated Ar ion beam milling. The end result is a precisely delayered device without sample preparation-induced artifacts suitable for identifying defects during physical failure analysis.

Abstract This paper evaluates the use of plasma etching for preparing TEM specimens to analyze high aspect ratio 3D NAND integrated circuits. By controlling plasma etching parameters, a relatively high material removal rate could be obtained. Moreover, through the control of etch time, the top region of the test specimens could be completely removed down through the expected number of layers, making it possible to resolve details throughout the entire sample, particularly in the middle region of the 3D NAND, using TEM cross-section analysis.

Abstract This paper evaluates the use of nanomilling and STEM imaging to analyze failure mechanisms in sub-50 nm InP HEMTS. The devices were life tested at elevated temperatures and biases and their electrical characteristics were measured at each stress interval. Devices that were damaged were investigated further to assess the underlying failure mechanism. Advanced microscopy with sub-nm resolution was employed to examine the physical characteristics of the failed HEMT devices at the atomic scale. As the paper explains, the examination was conducted using a focused ion beam/scanning electron microscope (FIB/SEM), an Ar gas ion nanomill, and STEM imaging.

Abstract IC camouflaging has been proposed as a promising countermeasure against reverse engineering. Camouflaged gates contain multiple functional device structures, but appear as a single layout under microscope imaging, thereby concealing circuit functionality. The recent covert gate camouflaging design comes with a significantly reduced overhead cost, allowing numerous camouflaged gates in circuits which improves resiliency against invasive and semi-invasive attacks. Dummy inputs are used in the design, but SEM imaging analysis has only been performed on simplified contact structures so far. In this study, we fabricated real and dummy contacts in different structures and performed a systematic SEM analysis to investigate contact charging and passive voltage contrast. Machine learning based pattern recognition was also employed to examine the possibility of differentiating real and dummy contacts. Based on our experimental results, we found that the difference between real and dummy contacts is insignificant, which effectively prevents SEM-based reverse engineering.

Abstract In this paper, we demonstrate with a case study on a nanocapacitor, the capability of transmission electron microscopy in electron holography mode to be a unique in-situ technique for mapping electric fields and charge distributions on a single device. Such precision is necessary to keep pace with shrinking device dimensions and the ever increasing complexity of device architectures.

Abstract In this work, we investigate mushroom type phase-change material (PCM) memory cells based on Ge 2 Sb 2 Te 5 . We use low-angle annular dark field (LAADF) STEM imaging and energy dispersive X-ray spectroscopy (EDX) to study changes in microstructure and elemental distributions in the PCM cells before and after SET and RESET conditions. We describe the microscope settings required to reveal the amorphous dome in the RESET state and present an application example involving the failure analysis of a PCM test array made with devices fabricated at IBM’s Albany AI Hardware Research Center.

Abstract An experimental study was undertaken to determine the minimum level of leakage or shorting current that could be detected by electron-beam induced resistance change (EBIRCH) analysis. A 22-nm SRAM array was overstressed with a series of gradually increasing voltage biases followed by EBIRCH scans at 1 V and 2-kV SEM imaging until fins were observed. It was found that the fins of a pulldown device could be imaged by EBIRCH at just 12 nA of shorting current, representative of a soft failure. Stressing the sample at higher voltages eventually created an ohmic short, which upon further investigation, strongly suggested that the Seebeck effect plays a significant role in EBIRCH analysis.

Abstract In this paper, we describe the difference between oscilloscope pulsing tests and waveform generator fast measurement unit (WGFMU) tests in analyzing high-resistance defects in DRAM main cells. Nanoprobe systems have various constraints in terms of pulsing whether it involves an oscilloscope or pulse generator. There are certain types of devices, such as DRAM cells, for which these systems are ineffective because saturation currents are too small. In this paper, we address this constraint and propose a new way to conduct pulsing tests using the WGFMU's arbitrary linear waveform generator in combination with an electro-optical nanoprobe.

Abstract This paper describes a procedure for preparing packaged GaN devices for photon emission microscopy from the backside, which has proven to be an effective method for isolating faults. The deprocessing technique was developed for GaN devices formed on thick p ++ silicon substrates mounted in quad-flat no-lead (QFN) packages connected by gold wires. It consists of mechanical polishing, which removes backside metal and packaging material, and selective etching, which quickly etches the silicon while leaving the gold wires intact for electrical measurements. The authors describe each step of the process in detail and explain how emission spots are marked with a UV laser and analyzed in a FIB-SEM system to determine the underlying cause of failure.

Abstract This paper presents a large-volume workflow for fast failure analysis of microelectronic devices. The workflow incorporates a stand-alone ps-laser ablation tool and a FIB-SEM system. As implemented, the picosecond laser is used to quickly remove large volumes of bulk material while the Xe plasma FIB provides precise end-pointing to the feature of interest and fine surface polishing after laser ablation. The paper presents several application examples, including a full workflow to prepare artefact-free, delamination-free cross-sections in an AMOLED mobile display and the preparation of devices and packages (including flip chips) of varying size. It also covers related issues such as CAD navigation, data correlation, and the use of bitmap overlays for end-pointing.

Abstract Vertical-cavity surface-emitting lasers (VCSELs) have many advantages over edge-emitting devices, but they tend to be more sensitive to increasing current density both in lifetime and reliability. To better understand this relationship, the authors investigated the cause of 35 failures involving GaAs-based oxide-confined VCSELs. This paper presents a summary of the procedures, methods, and equipment used, the defects and damages observed, and the root causes behind each failure. The authors followed a standard failure analysis workflow consisting of PEM and OBIRCH fault isolation, plan view TEM to confirm the location and distribution of defects, and cross-sectional TEM (XTEM) to determine the profile of a defect at a specific site. All failures examined could be attributed to one of four basic failure mechanisms: burnout due to ESD, dislocations, oxide diffusion, and oxide delamination.

Abstract Defects associated with metal-insulator-metal (MIM) capacitor failures can be difficult to locate using conventional fault isolation techniques because the capacitors are usually buried within a stack of back-end metal layers. In this paper, the authors explain, step by step, how they determined the cause of MIM capacitor failures, in one case, in an overvoltage protection device, and in another, a high-speed digital isolator circuit. The process begins with a preliminary fault isolation study based on OBIRCH or PEM imaging followed by more detailed analyses involving focused ion beam (FIB) cross-sectioning and delayering, micro- or nano-probing, resistive or voltage contrast imaging, and other such techniques.

Abstract This paper presents an alternative approach for analyzing complex scan chain failures in which there are multiple candidates that could be the root cause. It demonstrates the approach on an automotive IC with several failing flip-flops. An analysis of the interconnections shared by the failing devices reveals a common clock branch where the root cause is likely to reside. Photo-emission microscopy (PEM) is then used to verify the existence of a defect which, based on passive voltage contrast, is determined to be an open path.