As devices shrink, mitigating off-state power consumption has become a major concern for dynamic random access memory (DRAM) product development. The interface trap induced reduction of the retention time of DRAM cells has become increasingly critical due to aggressive device shrinkage. In this paper, the influence of reliability evaluation after device manufacturing on the number of interface traps in buried-channel-array-transistors and the optimal H 2 annealing temperature were investigated for the reduction of trap-induced leakage currents that cause retention time degradation in DRAM cells. This study is expected to solve the problem of retention time and off-state power consumption caused by interface traps and to be utilized as a cornerstone for next-generation DRAM development.

Hot electron induced beta degradation has been observed from fiber optic transistors after multiple parametric testing. Beta degradation originated from increasing base leakage current due to the multiple testing. Base leakage current increases were directly related to the hot electron phenomenon at Si-SiO2 interface layer. The hot electron effect broke down the trivalent silicon and its hydrogen compounds (SisH) at the interface layer, which created mobile interstitial hydrogen atoms (Hi) and trivalent silicon atoms Si* (interface trap charges) at the same time. Typically, the SisH forms during the post metallization anneal. This paper will outline the following topics: 1.) The generation of mobile hydrogen atoms and trap charges at the Si-SiO2 interface due to the hot electron phenomenon and its relationship to transistor beta degradation. 2.) A quantitative analysis of hydrogen atoms measured by Secondary Ion Mass Spectrometry (SIMS), and a direct relationship model between beta degradation and hydrogen profiles at the interface layer. 3.) Experimental result showing transistor beta recovery as well as the repopulation of the hydrogen atoms at the interface layer after low temperature annealing (150 °C to 200 °C bake).