Presentation slides for the ISTFA 2024 Tutorial session “Non-Destructive Defect Localization by Acoustic Microscopy.”

Presentation slides for the ISTFA 2024 Tutorial session “Correlative Microscopy: In-Situ AFM-in-SEM Introduction, Capabilities, and Case Studies Semiconductor Materials and Batteries.”

Presentation slides for the ISTFA 2024 Tutorial session “Review of Scanning Probe Microscopy Methods for Failure Analysis (2024 Update).”

Presentation slides for the ISTFA 2024 Tutorial session “Transmission Electron Microscopy.”

Presentation slides for the ISTFA 2024 Tutorial session “TEM Sample Preparation for Electron Microscopy Characterization and Failure Analysis of Advanced Semiconductor Devices.”

Presentation slides for the ISTFA 2024 Tutorial session “Advanced FIB/SEM Sample Preparation and Analysis Techniques (2024 Update).”

Presentation slides for the ISTFA 2024 Tutorial session “Basics and Current Aspects of Scanning Electron Microscopy.”

Presentation slides for the ISTFA 2024 Tutorial session “Transmission Electron Imaging AND Diffraction in an SEM (aka, STEM-in-SEM): What, Why, and How To Do This in Your Microscope.”

Presentation slides for the ISTFA 2024 Tutorial session “Atom Probe Tomography: Introduction and Applications to SEMI.”

In DRAM devices, many failures only appeared in a specific operating state on chips during functional tests. Dynamic photon emission microscopy (D-PEM) is a useful technique in failure analysis for emitted photons when the device under test (DUT) is electrically exercised. Therefore, D-PEM analysis combined with specific external triggers in functional test can activate the chip, and thereby expand the range of detectable defects and increase the chances of finding a specific failure mode. In this study, we will discuss various cases of external triggers applied from the tester. This method can be used to detect emission which did not show up in conventional test condition in PEM method for localizing active fails in DRAM. Then, after localizing the site of failure, more detailed physical visualization by Focused Ion Beam (FIB) cross section image, Transmission Electron Microscope (TEM), and Energy Dispersive X-ray microscopy (EDX) revealed main causes of failure. We believe that our method could be a future solution for increasingly difficult and diverse failures modes in the DRAM industry.

In the ever-increasing complexity of today’s state-of-the-art semiconductor structures, it is desirable to seek any advantage in the fault isolation and analysis paradigm to improve time to data. This paper discusses one such improvement where it is shown to be possible to target silicon (Si) devices, their metal contacts, or any other location in the wafer stack in a SRAM test structure from metal level 7 (M7) for transmission electron microscopy (TEM) sample fabrication using a modified sample geometry, focused ion beam (FIB) software targeting tools, and planning for failure analysis at the mask design stage. Electron beam inspection data was used to drive back to the location of interest in this example. The subsequent analysis shows a silicon and oxygen rich material creating an open contact defect signature.

The TEM sample preparation by Plasma focused ion beam (PFIB) for a 3D NAND sample with high aspect ratio (HAR) was investigated. Through the PFIB window delayering method, a nearly curtain-free and uniform thickness of TEM lamella could be obtained, addressing the issue of curtaining effectively. Moreover, the pre-treatment step for preparing the chunk of the region of interesting (ROI) out from wafer can be performed by PFIB automated procedures, which could promote the sample preparation efficiency. Through the PFIB window delayering method, TEM analysis of large-area HAR 3D NAND nanostructures becomes achievable.

Time-resolved emission microscopy (TREM) enables non-intrusive failure analysis of integrated circuits through photoemission detection at picosecond resolution. While photoemission occurs in both functional and faulty ICs, certain emission patterns distinctively indicate device defects. The primary mechanism driving this phenomenon is hot carrier luminescence in silicon, where carriers with excess kinetic energy release photons through intraband transitions. In CMOS logic, these emissions occur when MOSFETs switch between logical states, generating drain-to-source current flow. However, modern large-scale ICs present unique challenges for photoemission analysis: their lower operating voltages and reduced switching currents result in fewer photon emissions, predominantly in the infrared spectrum. We address these limitations by implementing superconducting-nanowire single-photon detectors (SNSPDs), enabling high-sensitivity photoemission microscopy for advanced IC failure analysis.

Failure analysis for gate oxide breakdown is increasingly challenging as technology advances to smaller technology nodes. Previously, the cross-sectional passive voltage contrast (XPVC) technique has been successfully utilized in mature technology nodes to isolate gate oxide breakdown locations in complex polysilicon gate structures of planar transistors. However, as semiconductor technology advances, more intricate transistor structures such as FinFET are employed to improve device performance. This paper focuses on the application of the XPVC technique to metal gate structures and examines the challenges associated with its implementation in advanced technology nodes. We demonstrate the applicability of this method in 14nm FinFET devices in simulated gate oxide breakdown experiments showcasing successful sample preparation for subsequent Transmission Electron Microscopy (TEM) analysis.

We introduce a novel piece of hardware that allows researchers to extend a nanomanipulator needle further into the vacuum chamber of a dual beam FIB SEM without venting the system. This hardware innovation will elevate throughput and diminish the instrument's downtime, which is pivotal for transmission electron microscope (TEM) sample preparation—a process integral to semiconductor manufacturers where the demand for TEM samples is high due to their necessity for process characterization and failure analysis of integrated circuits. Traditionally, the manipulator needle shortens with each sample preparation, ultimately reaching a mechanical limit that necessitates system venting to install a new needle. This hardware innovation allows users to feed out more needle length into the vacuum chamber by twisting a knob on the outside of the FIB SEM.

We present a study of dislocation conductivity under forward bias in p-GaN/AlGaN/GaN heterojunctions on a GaN-on-Si substrate, which are part of every p-GaN HEMT structure. Conductive atomic force microscopy (C-AFM) is combined with structural analysis by scanning transmission electron microscopy (STEM) and defect selective etching (DSE). The density of conductive TDs was found to be 5 × 10 6 cm -2 , using semi-automatic measurements to gather larger statistics on a delayered HEMT sample. IV measurements show a shift in turn-on voltage at the leakage positions. To characterize the type of the conductive TDs, DSE with a KOH/NaOH melt was used. Three distinct etch pit sizes were observed after 5 s etch time, with large, medium and edge pits according to STEM characterization seemingly corresponding to screw, mixed and edge TDs, respectively. However, characterization by DSE etch pit size alone was found to be unreliable, as STEM TD typing of seven conductive TDs using two-beam diffraction conditions revealed mostly pure screw and mixed-type dislocations with medium-sized etch pits as origin of the observed leakage current. Our work highlights the limitations of DSE as a characterization method and recommends additional validation by STEM for each new material system, investigated layer, and etching setup. The implications of finding conductive TDs with screw-component under low forward bias conditions on device behavior and the limitations of the C-AFM method are discussed. Based on the results, it is not anticipated that the identified conductive TDs will have a substantial effect on a GaN HEMT device. Overall, this study provides important insights into the electrical properties of TDs and offers useful recommendations for future research in this area.

Advanced semiconductor devices are disrupting traditional failure analysis workflows and creating demand for instrumentation that enables flexible capabilities to address these technology inflections. Such trends can be observed across multiple development areas, including faster processing, increased memory bandwidth, and power delivery. In every case, shrinking structures, complex packaging architecture, and advanced materials drive the need for efficient, precise targeting for regions of interest (ROI) over a wide range of length scales. An important example is the implementation of wide-bandgap (WBG) semiconductors, such as SiC and GaN, in advanced power devices. Various complexities are introduced, not only in device architecture, but also in defectivity analysis by conventional methods. As a result, high quality and high throughput failure analysis is achieved with specialized use of several plasma focused ion beam (PFIB) species best suited to these materials. Here we demonstrate such sample preparation for workflows involving electrical failure analysis (EFA) and localization, cross-sectional and volume analysis using scanning electron microscopy (SEM), as well as lamella preparation for transmission electron microscopy for physical failure analysis (PFA).

Soft defects—failures that manifest only under specific voltage, temperature, or frequency conditions—require specialized fault isolation techniques for accurate characterization. This paper demonstrates thermal response failure localization using scanning electron microscope (SEM) nanoprobing with an integrated thermal stage. While nanoprobing typically serves as the final step in fault isolation failure analysis (FIFA), thermal nanoprobing is essential for characterizing temperature-dependent parametric defects by enabling measurements at both passing and failing temperatures. We present three case studies: a "worse at cold" failure reproduction, a parametric root cause identification through thermal characterization, and a complex thermal failure that was uniquely isolatable through thermal nanoprobing. These cases illustrate the technique's effectiveness in analyzing temperature-dependent defects that occur outside room temperature conditions.

Electrical characterization is a critical step in the failure analysis workflow, a sequence that often ends in high-resolution imaging in the transmission electron microscope (TEM). Scanning TEM electron beam-induced current (STEM EBIC) is a technique that effectively combines these methods by performing electrical characterization at each imaging pixel, with the electron beam acting as a local current source. This work highlights the specimen preparation technique using the Ga FIB system followed by post-FIB Ar ion milling for STEM EBIC analysis. We present STEM EBIC as a technique to evaluate the surface quality of the specimens and to characterize the electronic properties of advanced devices at high resolution. With STEM EBIC, inactive and active finFET structures were clearly distinguished and improvements in sample quality from post-FIB Ar ion milling were evident.

We demonstrate the effectiveness of combining top-down and cross-sectional electron beam induced current (EBIC) imaging with SEM nanoprobe analysis to identify subtle front-end defects in advanced FinFET technology. Our approach successfully localized a novel fin nanocrack defect that had previously eluded detection through conventional TEM imaging. This systematic resistive pMOS failure, observable only in memory arrays at 150°C, exemplifies the power of EBIC as an alternative to scanning capacitance microscopy for detecting dopant anomalies and subtle defects. The sample preparation and EBIC methodologies presented here are broadly applicable across CMOS technologies, offering a versatile approach to defect analysis.