Hard failures, especially the Stuck at Reset failures insensitive to voltage, frequency, and temperature, are among the toughest to debug using the conventional Electrical Fault Isolation Methodology. These types of failures have no test data and no diagnostic information. Because of the failure being stuck at the reset sequence and being a hard failure, methodologies like Laser-Assisted Device Alteration (LADA) cannot be carried out. Photon Emission Microscopy (PEM) may exhibit numerous differences for good vs. bad die, however, most emission signatures typically indicate where IP is stuck in reset but do not indicate the actual root cause. Laser Voltage Probe (LVP) is the most logical way to proceed, but since Power-on Reset (POR) signals typically transition only once per test in conjunction with hard power cycling, the LVP averaging became very difficult as the hard power cycling increased the time of the loop drastically. This paper discusses a novel methodology of modulating power supply voltages within a looping pattern to optically probe the critical internal POR signal transitions effectively and debug the power sequencing of the device. This method is carried out through a custom test setup where a particular power supply of interest is modulated within the test loop without powering down other supplies connected, thereby avoiding the time penalty required for complete power down and power up. The method also synchronizes internal signals associated with POR to a tester-generated trigger in order to successfully obtain recognizable internally extracted POR-associated waveforms. This methodology is conveyed by explaining a complex functional failure analysis case study while highlighting where conventional failure analysis methods could not be used directly to identify the root cause of failure. This paper also describes another case study to explain how parametric information, such as the current profile using the current probe obtained during the test on a pass vs. fail device, can provide valuable information and help debug stuck-in reset failures.

Power MOSFETs are electronic devices that are commonly used as switches or amplifiers in power electronics applications such as motor control, audio amplifiers, power supplies and illumination systems. During the fabrication process, impurities such as copper can become incorporated into the device structure, giving rise to defects in crystal lattice and creating localized areas of high resistance or conductivity. In this work we present a multiscale and multimodal correlative microscopy workflow for the characterization of copper inclusions found in the epitaxial layer in power MOSFETs combining Light Microscopy (LM), non-destructive 3D X-ray Microscopy (XRM), Focused-Ion Beam Scanning Electron Microscopy (FIB-SEM) tomography coupled with Energy Dispersive X-ray Spectroscopy (EDX), and Transmission Electron Microscopy (TEM) coupled with Electron Energy Loss Spectroscopy (EELS). Thanks to this approach of correlating 2D and 3D morphological insights with chemical information, a comprehensive and multiscale understanding of copper segregations distribution and effects at the structural level of the power MOSFETs can be achieved.

Static random-access memory (SRAM) is a type of device that requires the highest reliability demands for integration density and process variations. In this study, we focus on single bit cell SRAM failures. These failures can be categorized as Hard bit cell failure, where bit cells fail the read or write operation under both higher and lower supply voltages, and Soft Bit cell failure, where failures occur at either higher or lower voltage. The analysis on SRAM Soft failure is further divided as VBOX High and VBOX Low failure, which depends on the failure mode supply voltage. With transistor dimensions continuously shrinking, the analysis of SRAM errors imposes tremendous challenges due to their small footprint. In this paper, a thorough failure analysis procedure is described for solving an SRAM yield loss issue. Different analysis techniques were applied and compared to narrow down the failure to the final root cause, including nanoprobing, Focus Ion Beam (FIB) cross-section, Scanning Spreading Resistance Microscopy (SSRM), Transmission Electron Microscopy (TEM), Electron Energy Loss Spectroscopy (EELS), Scanning Capacitance Microscopy (SCM), and stain etch.

This paper presents a root cause analysis case study of defective Hall-effect sensor devices. The study identified a complex failure mode caused by chip-package interaction, which has a similar signature to discharging defects such as ESDFOS. However, the study revealed that the defect was induced by local mechanical force applied to IC structures due to the presence of large irregular-shaped filler particles within the mold compound. Extensive failure analysis work was conducted to identify the failure mode, including the development of a new backside analysis strategy to preserve the mold compound during IC defect localization and screening. A combination of different failure analysis techniques was used, including CMP delayering, PFIB trenching, SEM PVC imaging, and large area FIB cross-sectioning. The study found that the mold compound of the package caused thermos-mechanical strain onto the silica filler particle due to epoxy shrinkage during the molding process. Additionally, extra-large, irregularly shaped filler particles (called twin particles), located on top of the chip surface, can cause locally high compression stresses onto the IC layers, initiating cracks in the isolation layers under certain conditions forming a leakage path over the time. Thermo-mechanical finite element analysis was applied to verify the mechanical load condition for these large irregular-shaped filler particles. As a result, an additional polyimide layer was introduced onto the IC to mitigate the mechanical stress of mold compound particles to avoid this failure mode.

Photon Emission Microscopy (PEM) is a popular technique for microelectronics failure analysis by detecting the photon emission from a defective circuit, when a failing device is electrically exercised at certain voltage. The photon emission contains physical location information, photon emission spectral information and photon emission intensity information. People often use the physical location information to localize a defective circuit and guide the follow-up physical failure analysis to find the defects. However, this procedure does not always work. Sometimes, it shows no defect found (NDF). In this paper, we propose a new computer vision-based analysis of the photon emission intensity for identifying the root cause of the excessively high IDDQ at elevated Vdds. The procedure includes collecting photon emissions at different Vdds and a follow-up photon emission intensity analysis with computer vision techniques. The procedure was applied on a case of microprocessor chip. After analyzing the dependencies of photon emission intensity on Vdd for 4 types of circuits, it was concluded that the SRAM circuit leakage is the root cause of the excessively high IDDQ at elevated Vdd.

We present the first experimental demonstration of on demand bit-level Static Random Access Memory (SRAM) validation and isolation through the exploitation of a continuous wave (CW) 785nm Laser-Induced Fault Analysis (LIFA) system. Through careful test pattern edits and the observation of a simple pass/fail flag, the ability to spatially map the physical location of pre-selected bits in 40nm, 16nm, and 5nm SRAM arrays using correlation units is confirmed. This work demonstrates a novel and highly-efficient methodology for rapid bit-level logical-to-physical identification. It also improves localization efficacy over conventional bitmap validation best-known methods (BKM) which typically rely on post-fail Photo-Emission Microscopy (PEM) and/or Soft Defect Localization / Laser-Assisted Device Alteration (LADA) performed on an actual fail unit. This new technique re-defines the state-of-the-art in SRAM bitmap validation and localization and offers a pathway to significantly improve cycle time for both product bitmap qualification and subsequent root cause identification.

It has been a challenge to perform failure analysis for miniaturization of process node technology in high-speed transceiver. Failure analysis plays an important role in root cause analysis to enable R&D, product quality & reliabily improvement. This paper demonstrated an effective FA approach on a real case with ADPLL functional failure within a high-Speed transceiver in complex sub-nano FPGA. This successful case is achieved by incorporating Analog Probe (APROBE), Infrared Emission Microscopy (IREM), extensive layout study, delayering, Nanoprobing and Scanning Electron Microscopy (SEM) for defect localization.

The growing demand for flash memory in the artificial intelligence and big data industries has driven the development of Negative AND (NAND) gates. To increase yield and cost competitiveness, NAND has evolved to stack gates vertically, resulting in vertical NAND (VNAND) technology. However, this advancement has led to challenges, such as high aspect ratio-related difficulties and word line (WL) metal Tungsten (W) substitution process defects. In this study, we investigated Voltage Blocking Oxide Barrier (VBB) defects in VNAND cells under high-temperature conditions using in-situ heating TEM. By artificially creating VBB defect environments within VNAND cells and analyzing structural and chemical changes, we identified VBB defects expression phenomenon caused by residual HF(g) in metal voids during post-metal replacement processes. Our findings offer insights into defect-inducing heat treatment conditions affecting VBB in VNAND devices and propose directions for next-generation NAND flash processes.

As technology nodes continue to shrink, Scanning Electron Microscopy (SEM) inspection and electrical characterization of transistors has increased in difficultly. This is particularly true with early back end-of-line (BEOL) features like metal and via layers which are traditionally imaged at 3-5 keV. At these layers, this energy is capable of beam contamination, introducing electrical complications particularly with transistor probing. This electrical data is necessary to characterize subtle defects at front end-of-line (FEOL). Thus, the implementation of beam deceleration for the inspection of these layers provides a useful combination of low landing energy and higher image quality. This technique proves to aid in preserving the ability to electrically characterize any defect at the subsequent layers beneath. This increases the quality of the Physical Failure Analysis (pFA) workflow when implemented at early BEOL layers by providing higher quality images as well as preserving the electrical properties of the transistors for subtle FEOL defect characterization.

High-speed time-resolved emission analysis is an attractive failure analysis technique because of its non-invasiveness. Super-conductive nanowire single photon detector (SNSPD or SSPD) is a key candidate of key device for time-resolved emission analysis. In this paper, we demonstrate time-resolved emission and its application of spatial resolution enhancement. We could confirm that time-resolved emission imaging can enhance spatial resolution by simple mathematical operations compared to static emission analysis, which is effective for finding emission spots before detailed time-resolved data investigations.

Scanning Electron Microscope (SEM) is a valuable tool for measuring Critical Dimensions (CD) of semiconductor devices at the nanometer scale. Vertical SEM application is one of the applications for high accurate CD measurement on cross-sectional surface. Even a slight stage tilt angle change of the vertical sample can impact CD values in nanometer scales of the sample surface features. For accurate CD measurements, it is essential to ensure the sample is positioned correctly to acquire the sample image. However, it is challenging to achieve a perfect alignment with the incident beam direction and the accurate perpendicular direction on the cross-sectional surface on SEM tool. To achieve an ideal vertical positioning of the sample, the combination of the stage tilt axis and stage rotation axis can be used. Exact calculation is required to achieve an accurate CD measurement. In this paper, a calculation method of the tilt angle correction to achieve a perpendicular angle to the surface and its verification method are described. Reliable measurement can be achieved by employing an automated script for compensation. We also demonstrate an approach for highly reliable angle correction and improved metrology results in this paper.

Photoresist (PR) profiles tend to have deformation and shrinkage with typical transmission electron microscopy (TEM) sample preparation methods using a focused ion beam scanning electron microscope (FIB-SEM). As the temperature increases during the TEM sample preparation, it may lead to deformation and shrinkage in PR profiles. In this study, we analyze the impact when performing the sample preparation at a cold temperature using a cryo-FIB to minimize deformation and shrinkage issues. To test this methodology, the TEM sample preparation process was performed under different conditions. From these experiments, the TEM results with full cryo conditions showed that the PR line to space ratio was closest to the target, which is the sample’s real line to space ratio (1:1), and the bottom anti-reflective coating (BARC) shrinkage was minimized.

Advanced memory technologies are in demand with phase change memory (PCM) devices as a forefront candidate. For successful characterization by transmission electron microscopy (TEM) for failure analysis and device development, an accurate and controllable thinning of TEM specimens is critical. In this work, TEM specimens from a GeTe-based PCM device at a partial SET state were prepared using a Xe plasma focused ion beam (pFIB) and polished to electron transparency using Ar ion beam milling. We will highlight the differences between Ga focused ion beam (FIB) and Xe pFIB TEM specimen preparation, the benefits of post-pFIB Ar ion beam milling, and show TEM results of the effects of partial SET programming of the GeTe PCM device.

As integrated circuit (IC) feature dimensions have shrunk, the need for precise and repeatable sample preparation techniques has increased. In this work, the process of preparation of ultrathin planar-to-cross-section conversion transmission electron microscopy (TEM) samples using a gallium dual-column focused ion beam (FIB)/scanning electron microscope (SEM) system is examined. Sample preparation technique in this paper is aimed at repeatably isolating features in the 5-30 nm range, while limiting common issues such as amorphization, lamella warpage, and the curtain effect (or “curtaining”). This can be achieved through careful selection of FIB parameters including ion beam energy, ion beam current, stage tilt, and deposited protective layer materials and thicknesses, which are all discussed in this work.

Continued advancements in the architecture of 3D packaging have increased the challenges in fault isolation and failure analysis (FA), often requiring complex correlative workflows and multiple inference-based methods before targeted root cause analysis (RCA) can be performed. Furthermore, 3D package components such as through-silicon-vias (TSVs) and micro-bumps require sub-surface structural characterization and metrology to aid in process monitoring and development throughout fabrication and integration. Package road-mapping has also called for increased die stacking with decreased pitch, TSV size, and die thickness, and thus requires increased accuracy and precision of various stateof- the-art analytical techniques in the near future. Physical failure analysis (PFA), process monitoring, and process development will therefore depend on reliable, high-resolution data directly measured at the region of interest (ROI) to meet the complexity and scaling challenges. This paper explores the successful application of plasma-FIB (PFIB)/SEM techniques in 2D and 3D regimes and introduces diagonal serial sectioning at package scales as a novel approach for PFA and metrology. Both 2D and 3D analysis will be demonstrated in a high bandwidth memory (HBM) package case-study which can be applied more broadly in 3D packaging.

TEM automation is dedicated to providing high-volume, fast and precise TEM data to enable semiconductor manufacturers to develop and control fabrication processes. It automates TEM operation and measurement procedures, and minimizes the requirements of user training. Traditionally, recipes are required for each specific structure, and Automatic TEM Imaging and Metrology had individual recipes for each structure, respectively and separately. TEM professionals review structures and TEM images and manually assign imaging and metrology recipes one by one. After metrology, it is tedious to manually check mis-measurement of hundreds of TEM images and Critical Dimensions (CDs). In this study, An Intelligent TEM automation process was developed by machine learning process that could “fully” automatically conduct TEM Analysis from Imaging to Metrology starting right after TEM holder insertion without human intervention. It is not limited to automatically prepared TEM samples and also works for manually prepared samples. TEM Auto Metrology is carried out automatically right after Auto Imaging in the background. After that, Auto capturing of mis-measurements can be carried out automatically to catch problematic metrology images and CDs as an invaluable complement. As a result, the whole workflow was streamlined, with better efficiency and accuracy achieved.

Focused-Ion Beam Scanning Electron Microscopy (FIB-SEM) tomography is a high resolution three-dimensional (3D) imaging method with applications in failure analysis and metrology of semiconductor devices. For the smallest logic and memory structures currently in use, it requires single-digit nanometer 3D resolution. In this resolution range, avoiding distortion artifacts in the data becomes crucial. We present examples and discuss ways to reduce the likelihood of such artifacts during the data acquisition, as well as how to mitigate them in post-processing, and therefore increase the data quality.

Failure analysis of small contamination at the surface and sub-surface interface represents a major set of common microelectronics and semiconductor issues. The application of O-PTIR spectroscopy analyses provides flexibility to sample preparation and improves sensitivity to very small levels of contamination even below <1 micron in layers or particles on or just below the surface. The detection of this contamination can be limited if only bright field imaging is used to contrast the region of interest (ROI) and the surrounding structure. Adding fluorescence microscopy is an additional imaging technique that adds another layer of chemical specificity and provides locations of unseen ROI’s for additional IR and Raman spectral analysis.

An approach to overcome barriers to practical Compressed Sensing (CS) implementation in serial scanning electron microscopes (SEM) or scanning transmission electron microscopes (STEM) is presented which integrates scan generator hardware specifically developed for CS, a novel and generalized CS sparse sampling strategy, and an ultra-fast reconstruction method, to form a complete CS system for 2D or 3D scanning probe microscopy. The system is capable of producing a wide variety of highly random sparse sampling scan patterns with any fractional degree of sparsity from 0- 99.9% while not requiring fast beam blanking. Reconstructing a 2kx2k or 4kx4k image requires ~150-300ms. The ultra-fast reconstruction means it is possible to view a dynamic reduced raster reconstructed image based upon a fractional real-time dose. This CS platform provides a framework to explore a rich environment of use cases in CS electron microscopy that benefit from the combination of faster acquisition and reduced probe interaction.

This paper investigates the enhanced inspection of High Bandwidth Memory (HBM) stacks using Scanning Acoustic Microscopy (SAM). As the multi-layer structure is quite complex, sophisticated signal processing methods are employed. To improve detection capabilities and inspection time, the Synthetic Aperture Focusing Technique (SAFT) is utilized. In contrast to previous trials applying SAFT on SAM data, this contribution introduces Near Field SAFT. Reconstruction is also performed for layers between the transducer and its focus, in the near field of the transducer. This approach allows for measurements with common working distances, providing higher frequencies and improved resolution. Systematic evaluations are conducted on various measurement setups and transducers with different center frequencies and focal lengths in order to determine the most optimal measurement setup.