In this study, a 65nm product level low yield case has been investigated and its failure mechanism was identified. Root cause analysis was discussed and concluded. The product has been hit with ATPG failure with a unique wafer map signature - a butterfly pattern. Tools commonality and timeframe analysis show that the highly suspected process is the Metal1 Cu seed PVD step. To understand the failure mechanism and its root cause, product level FA was needed. However due to its functional failure property, the conventional EFA is not applicable in this case. Instead GDS study was performed to isolate the failure sites. Subsequently physical FA analysis was carried out at the identified sites to reveal its failure mechanism. Metal1 void was observed on the sidewall of the metal1. Meanwhile, a very interesting phenomenon was observed. If die was selected on the left part of the butterfly pattern, the void would be on the right side sidewall of the metal. If the die was selected on the right part, the void would be on the left side sidewall of the metal1. All of the voids were towards wafer center. After in-depth study of the PVD process, we suspect the pass die could also have void. These voids must be also towards wafer center. Subsequent PFA on good unit confirmed our suspect. The more detailed mechanism of the void formation was discussed and evidences supporting our analysis are to be presented in the paper. Nevertheless, the butterfly pattern is still a question in our mind. After in-depth analysis, we found the voids formation was associated with Metal1 orientation. Because of the horizontal orientation of Metal1, if the void happens it should locate in the end of the metal line in the butterfly area. While the majority of Via1/contact are stand on the line end, so the open Via1/contact failure will happen. For the die out of the butterfly area, the majority of the void locates in the sidewall of the metal line center. The majority Via1/contact are not stand in the center of the metal line center, of no Via1/contact open happen. But it is still has reliability concern. Much more detailed and in-depth mechanism is investigated in the paper. Moreover, improvement is also touched on. Systematic problem solving method is employed in this case. It is good reference for same kinds of failure analysis.

Sub-nanometer focused inert gas ions derived from a Gas Field Ion Source (GFIS) contain properties that can improve the dimensional and conductivity characteristics of ion beam deposited platinum circuit edit wiring. The following paper, presents ion interaction simulations that help provide insight into the factors which determine the ultimate wire width, resistivity, and metal deposition rates. An experimental result that has aided in the understanding of the primary wire width limiting mechanism is also presented. Finally, a description of the ion beam and precursor properties used for the platinum deposition is provided, a long with a discussion of the wire resistivity measurement technique and challenges. To conclude, the prospects for GFIS ion induced dielectric and metal deposition for circuit edit and nanofabrication applications are discussed.

We present an analysis of tungsten vias fabricated by a focused ion beam with regard to the understanding of circuit editing strategies. The growth rate of W is ~10 times faster in high aspect ratio vias than on flat surfaces, and W in vias has 4 at. % more C but only one-tenth the Ga of surface-deposited W. We propose that vias act like small Faraday cups, trapping the energy of the Ga+ ions and the reaction byproducts to enhance the growth rate of W and to increase the C to W ratio in vias compared to flat surfaces. The resistivity of W in the vias determined by a least squares fit to resistance data is 250μΩ-cm, unchanged from the resistivity of W deposited on a flat surface. The resistances of the vias fabricated in a SiO2 layer to contact an underlying Al sheet layer fit well to either of two models: 1) an effective area model that invokes resistive via sidewalls that do not participate in conduction, and 2) an contact resistance model that invokes tapered vias with a constricted W/Al contact area.

Circuit Edit (CE) through a conductor requires an insulator to isolate the connection transiting the conductor. We investigate several recipes to determine not just the optimum recipe but also the latitude to provide a means of throughput optimization for a given edit requirement. The results show that trade-offs in deposition rate, robustness and isolation quality can be made to enable this throughput optimization.

The effect of ash chemistries, N2/H2 and H2, on time-dependent dielectric breakdown (TDDB) lifetime has been investigated for Cu damascene structure with a carbon-doped CVD ultra low-k (ULK, k=2.5) intermetal dielectric. Two failure modes, interfacial Cu-ion-migration and Cu diffusion through the bulk intermetal ULK were attributed to the TDDB degradation for the H2 ash.The interfacial Cu-ion-migration was the only dominated failure mode for the N2/H2 ash. The nitrogen species in the N2/H2 plasma proved to be capable of forming a nitrided protection layer on the surface of the ULK. This nitrided layer suppressed further plasma damage during the ash process and thus lessened the TDDB degradation by preventing Cu diffusion through the bulk ULK.

Precision detection of endpoint after the milling has reached targeted conductor during circuit modification by focused ion beam system is important. While the sensitivity of the endpoint detection can be enhanced by improved secondary electron collection and sample absorbed current monitoring, a detailed understanding of the endpoint signal distribution within a high aspect ratio (HAR) via is of great interest. This article presents an alternative model of HAR via milling endpointing mechanism in which a phenomenon of spatial distribution of the endpoint information within the HAR via is explained based on sputtering of the material from the targeted metal line and redeposition of the spattered material on the via sidewalls. Increased emission of the secondary electrons, resulting from the subsequent bombardment of this conductive re-deposition by the primary ion beam, is detected as the endpoint. A methodology for the future experimental verification of the proposed model is also described.

This paper describes a novel method of sample preparation for Transmission Electron Microscope (TEM) analysis, particularly a technique for photoresist sample preparation for TEM analysis. In the analysis of an ultra large scale integrated (ULSI) circuit, the profile images of a ULSI circuit sample are crucial. In order to identify the tiny features of modern semiconductor devices clearly, TEMs are used because of their high spatial resolution. However, TEM analysis is not available for photoresist material, especially for a patterned photoresist layer, due to the difficulty in specimen preparation and its susceptibility to electron beam damage during TEM analysis. A critical step in preparing this type of TEM specimens is to deposit a conductive layer and a dielectric layer upon the patterned phototresist by a physical vapor deposition process at room temperature first, then followed by a focus ion beam (FIB) process. The exact profile of the patterned photoresist is kept, during specimen preparation and TEM analysis, by this modified method. Precise dimension measurements are then possible.

Backside photoemission microscopy [1-2] was used to analyze the major yield loss of a communication product fabricated with submicron CMOS process: functional failures of phase-lock-loop (PLL). The PLL block was covered by five metal layers and three of them were bulk metals. Based upon the backside photoemissions detected on the capacitor structures within the PLL block and the ruptures observed at the emission spots on the polysilicon and gate oxide or of the capacitor after physical deprocessing, the failure was proved due to the capacitor gate-oxide breakdown. This was believed to be caused by the plasma-induced-damage during high-density-plasma (HDP) CVD oxide deposition after the front-end processes, as only the lots from one HDP-CVD deposition equipment have very high percentage PLL functional failure. Subsequent machine commonality check did find non-uniform inter layer dielectric (ILD) thickness from this equipment, which indicated the non-uniform plasma intensity occurred during the ILD film deposition. This was further confirmed by the finding of a worn-out gas-shower-head in this system. The abnormal high density of plasma created extra charging and caused the PLL poly capacitor’s gate oxide breakdown due to the antenna effect. After replacing the gas showerhead, the failure disappeared and yield was back to normal. Through this low yield analysis, we demonstrated an effective application of backside photoemission microscopy to fab yield improvement.

Use of non-contact test techniques to characterize degradation of the Si-SiO2 system on the wafer surface exposed to a plasma environment have proven themselves to be sensitive and useful in investigation of plasma charging level and uniformity. The current paper describes application of the surface charge analyzer and surface photo-voltage tool to explore process-induced charging occurring during plasma enhanced chemical vapor deposition (PECVD) of TEOS oxide. The oxide charge, the interface state density, and dopant deactivation are studied on blanket oxidized wafers with respect to the effect of oxide deposition, power lift step, and subsequent annealing.

This paper explains how laser assisted deposition used in combination with focused ion beam (FIB) milling reduces turnaround time for complex circuit modifications. It presents the results of three case studies, characterizing the process and the effect of various processing parameters. The first case involves the creation of a low resistance path between internal signal lines using only laser techniques; the second case demonstrates the use of laser deposition to route interconnects, millimeters in length, between two complex FIB modifications; and the third case is designed to reproduce a charge build-up problem. The paper also discusses the use of gold as a deposition material.

The specimen preparation technique using focused ion beam (FIB) to generate cross-sectional transmission electron microscopy (XTEM) samples of chemical vapor deposition (CVD) of Tungsten-plug (W-plug) and Tungsten Silicides (WSi x ) was studied. Using the combination method including two axes tilting[l], gas enhanced focused ion beam milling[2] and sacrificial metal coating on both sides of electron transmission membrane[3], it was possible to prepare a sample with minimal thickness (less than 1000 A) to get high spatial resolution in TEM observation. Based on this novel thinning technique, some applications such as XTEM observation of W-plug with different aspect ratio (I - 6), and the grain structure of CVD W-plug and CVD WSi x were done. Also the problems and artifacts of XTEM sample preparation of high Z-factor material such as CVD W-plug and CVD WSi x were given and the ways to avoid or minimize them were suggested.