Presentation slides for the ISTFA 2024 Tutorial session “TEM Sample Preparation for Electron Microscopy Characterization and Failure Analysis of Advanced Semiconductor Devices.”

Presentation slides for the ISTFA 2024 Tutorial session “Advanced FIB/SEM Sample Preparation and Analysis Techniques (2024 Update).”

This presentation covers the basic physics needed to understand and to effectively apply backside IC analysis techniques to flip-chip packaged die. It describes the principles of light transmission through silicon and the factors that influence optical image formation from the backside of the wafer or die. It also provides information on the tools and techniques used to expose surfaces, regions, and features of interest for analysis. It describes the steps involved in CNC milling, mechanical grinding and polishing, reactive ion etching (RIE), laser microchemical (LMC) etching, and milling and etching by focused ion beam (FIB). It explains where and how each technique is used and quantifies the capabilities of different combinations of methods.

This presentation shows how transmission electron microscopy (TEM) is used in semiconductor failure analysis to locate and identify defects based on their physical and elemental characteristics. It covers sample preparation methods for planar, cross-sectional, and elemental analysis, reviews the capabilities of different illumination and imaging modes, and shows how beam-specimen interactions are employed in energy dispersive (EDS) and electron energy loss spectroscopy (EELS). It describes the various ways transmission electron microscopes can be configured for elemental analysis and mapping and reviews the advantages of scanning TEM (STEM) approaches. It also provides an introduction to energy-filtered TEM (EFTEM) and how it compares with other TEM imaging techniques.

This presentation provides an overview of chip-scale packages (CSPs) and the challenges they create for failure analysis. It begins with a review of stacked, multichip, and wafer-level packages, using images and illustrations to highlight complexities. It then presents examples of package-level failure mechanisms including various forms of cracking, inadvertent wire bond contact, and die-edge chipping. It likewise assesses die-level analysis challenges and provides practical solutions. The presentation also includes several case studies and describes new and emerging challenges.

There are several variants of artificial intelligence (AI) hardware structures that are under study by the semiconductor industry for potential use in complementary metal–oxide–semiconductor (CMOS) designs. This paper discusses some of the failure analysis challenges that have appeared in discrete test structures and test arrays developed as part of an exploratory phase-change memory (PCM) program at IBM's Albany AI Hardware Research Center.

Planar deprocessing is a vital failure analysis technique for semiconductor devices. The basic concept is to expose an area of interest (AOI) by removing unnecessary material while maintaining planarity and surface evenness. Finger deprocessing is a widely used material removal technique, particularly for fin field-effect transistors (FinFETs). Here, success depends on certain factors, one of which is the location of the AOI. If the AOI is near the edge of the chip, finger deprocessing can be very difficult because material removal rates are much higher there than at the center of the chip. Plasma focused ion beam (PFIB) planar deprocessing is the preferred solution in such cases, but many labs cannot afford a PFIB system. To address this challenge, a sample preparation method has been developed that uses dummy chips to effectively eliminate edges. With dummy chips placed edge-to-edge with test chips, planar deprocessing can be achieved using conventional finger deprocessing techniques. This paper describes the newly developed method, step by step, and presents two examples demonstrating its use.

Convention hand polishing, which is widely used for delayering, is becoming increasingly difficult as metal lines and stacks in semiconductor devices get thinner. For one thing, endpointing at the exact targeted layer and region of interest is a major challenge. The presence of cobalt and its propensity to oxidize, thus complicating electrical measurements, is another challenge. In this study, the authors demonstrate an alternative delayering method based on plasma focused ion beam (PFIB) milling aided by DX gas. The workflow associated with the new method is more efficient than that of conventional hand polishing and can help prevent cobalt oxidation.

With manufacturers now capable of creating transistors in the 5-7 nm node range, the ability to isolate, inspect, and probe individual metal and via layers is of the utmost importance for defect inspection and design validation. These isolated layers can be inspected for defects via SEM, provide design validation, or tested with electrical probing for failure analysis. The work herein describes a functional workflow that enables manufacturers to perform this kind of sample preparation in an automated fashion using plasma focused ion beam (FIB) technology. The workflow is scalable and can be used in both lab and fabrication environments.

This paper presents a method for determining positional variation and offsets in high aspect ratio etches used in the production of 3D NAND devices. The method uses a 3D fiducial as a positional reference in the field-of-view, which not only allows for high precision tracking of features through the depth of the device, but also aids in the alignment of images when performing 3D reconstructions. The workflow is based on plasma dual beam diagonal milling, which allows users to characterize structures through the device stack at a much higher throughput/slice than conventional methods, enabling enhanced process monitoring and control.

This paper discusses the development of an automated cell layer counting process for preparing 3D NAND flash memory samples for TEM analysis. In an initial proof-of-concept, several line markings were inscribed on the test device in evenly spaced intervals in order to evaluate its helpfulness for a human operator. A more automated procedure was then developed in which cell layers were counted to a desired target layer starting from a reference layer set by the operator. At that point, the operator could begin preparing the TEM sample.

This paper describes how electron beam induced current (EBIC) analysis is used to determine the doping profile of p-n junctions and identify defective devices. The limitations of both chemical etching and EBIC are discussed as is the use of ion milling as a potential method for enhancing resolution. The findings in this paper add to the understanding of EBIC and provide insights to further improvements in its use in failure analysis.

This paper explains how tunneling atomic force microscopy (AFM) was used to determine the cause of leakage in FinFETs along the boundary of SRAM cells. The leaking devices were electrically isolated using photoemission microscopy, but conventional FA techniques, including SEM and TEM imaging, found no structural abnormalities. Suspecting that the failures may be due to dopant-related issues, the authors obtained cross sections of both good and bad devices and scanned them in a tunneling AFM. The paper describes the sample preparation process and includes cross-sectional images showing the difference between good and bad transistors. In SRAM areas where no leakage occurred, the fins are well defined and evenly spaced. However, in the area where an emission spot was observed, two of the fins appear to be overlapping, the result of n-well implants that merged.

An image sensor module failed in the field and was returned showing functional issues and a supply-to-ground short. After the hard lens mounted over the imaging chip was removed, the short disappeared along with the functional issues. This paper explains how the authors were able to restore the failure mode and discover the underlying defect, via backside focused ion beam cross-sectioning, with minimal intrusion into the top-side package and silicon.

For unique single failures, which tend to be the case in customer return and reliability failures, selecting another sample or performing root cause deconvolution is not an option, and if diagnostic tests are not conclusive, it becomes necessary to extend the effectiveness of automatic test pattern generator (ATPG) diagnosis in order to determine the failure mechanism. This paper proposes a way to improve resolution using single-shot logic and high-resolution targeted patterns. Two cases are presented to demonstrate the approach and show how it performed on actual failing units.

This paper presents a development in semiconductor device delayering by broad ion beam milling that offers a uniform delayering area on a millimeter scale. A milling area of this size is made possible by the user's ability to position ion beams individually to cover the desired area. This flexibility in ion beam positioning also enables more precise targeting of an area of interest.

This paper presents a die-level sample preparation technique that uses selective etch chemistry and laser interferometry to expose the entire top metal layer surface for electrical fault isolation. It also describes a novel e-beam based probing technique called StaMPS which is used to isolate logic structure failures through SEM image contrasts. By landing SEM probe tips on exposed metal pads and controlling logic states via an applied bias, different levels of contrast are created highlighting structural failure locations. Die-level sample preparation combined with e-beam fault isolation optimizes turnaround time by delayering die in less than an hour and by locating several types of defects in a single sample.

Integrated circuit (IC) delayering workflows are highly reliant on operator experience to determine processing end points. The current method of end point detection during IC delayering uses qualitative correlations between the thickness and color of dielectric films observed via optical microscopy. The goal of this work is to quantify this relationship using computer vision. As explained in the paper, the authors trained a convolutional neural network to estimate the thickness of dielectric films based on images and measurements recorded during processing. The trained vision model explained 39% of the variance in dielectric film thickness with a mean absolute error of approximately 47 nm. The paper describes the entire workflow, including verification testing, and addresses the primary sources of error.

This paper presents a method that allows top view SEM inspection on GaN devices previously subjected to PEM analysis from the backside and the associated sample preparation procedures. By filling the backside cavity with glob-top resin and epoxying the device to a piece of silicon, it is possible to remove all covering layers with a sequence of wet etches. A dried Ag liquid strap eliminates SEM charging problems and backside laser marks are made visible from the front side using an IR wavelength. The paper describes each step of the process in detail along with the results of the frontside SEM inspection.

This paper describes optical and electron beam based fault isolation approaches for short and open defects in nanometer-scale through-silicon via (TSV) interconnects. Short defects are localized by photon emission microscopy (PEM) and optical beam-induced current (OBIC) techniques, and open defects are isolated by active voltage contrast imaging in a scanning electron microscope (SEM). The results are confirmed by transmission electron microscopy (TEM) cross-sectioning.