Gate oxide breakdown has always been a critical reliability issue in Complementary Metal-Oxide-Silicon (CMOS) devices. Pinhole analysis is one of the commonly use failure analysis (FA) technique to analysis Gate oxide breakdown issue. However, in order to have a better understanding of the root cause and mechanism, a defect physically without any damaged or chemical attacked is required by the customer and process/module departments. In other words, it is crucial to have Transmission Electron Microscopy (TEM) analysis at the exact Gate oxide breakdown point. This is because TEM analysis provides details of physical evidence and insights to the root cause of the gate oxide failures. It is challenging to locate the site for TEM analysis in cases when poly gate layout is of a complex structure rather than a single line. In this paper, we developed and demonstrated the use of cross-sectional Scanning Electron Microscope (XSEM) passive voltage contrast (PVC) to isolate the defective leaky Polysilicon (PC) Gate and subsequently prepared TEM lamella in a perpendicular direction from the post-XSEM PVC sample. This technique provides an alternative approach to identify defective leaky polysilicon Gate for subsequent TEM analysis.

Novel techniques to expose substrate-level defects are presented in this paper. New techniques such as inter-layer dielectric (ILD) thinning, high keV imaging, and XeF2 poly etch overflow are introduced. We describe these techniques as applied to two different defects types at FEOL. In the first case, by using ILD thinning and high keV imaging, coupled with focused ion beam (FIB) cross section and scanning transmission electron microscopy (STEM,) we were able to judge where to sample for TEM from a top down perspective while simultaneously providing the top down images giving both perspectives on the same sample. In the second case we show retention of the poly Si short after removal of CoSi2 formation on poly. Removal of the CoSi2 exposes the poly Si such that we can utilize XeF2 to remove poly without damaging gate oxide to reveal pinhole defects in the gate oxide. Overall, using these techniques have led to 1) increased chances of successfully finding the defects, 2) better characterization of the defects by having a planar view perspective and 3) reduced time in localizing defects compared to performing cross section alone.

Transmission electron microscope based elemental analysis techniques utilize X-ray photons in EDS and inelastically scattered electrons or the energy-loss electrons in electron energy-loss spectroscopy and energy-filtered transmission electron microscopy (EFTEM). This paper discusses the applications of EFTEM to visualize polysilicon defects, gate dielectric and silicon nanocrystals using inelastically scattered low energy-loss electrons. It focuses on features that are primarily composed of silicon and silicon-oxide. Various benefits of using plasmon energy-loss electrons to image silicon nanocrystals layer in thin film storage device are also outlined. Even though this work has focused on low-loss imaging of features and defects in the front-end of the process based on silicon/silicon-oxide integrated circuits, these techniques can also be applied to technologies based on other materials by selecting appropriate plasmon peaks corresponding to those materials.

Detection of both Insufficient Buried Contact (IBC) and cell-to-cell short defects is quite a challenging task for failure analysis in submicron Dynamic Random Access Memory (DRAM) devices. A combination of a well-controlled wet etch and high selectivity poly silicon etch is a key requirement in the deprocessing of DRAM for detection of these types of failures. High selectivity poly silicon etch methods have been reported using complicated system such as ECR (Electron Cyclotron Resonance) Plasma system. The fact that these systems use hazardous gases like Cl2, HBr, and SF6 motivates the search for safer alternative deprocessing chemistries. The present work describes high selectivity poly silicon etch using simple Reactive Ion Etch (RIE) plasma system using less hazardous gases such as CF4, O2 etc. A combination of controlled wet etch and high selectivity poly silicon etch have been used to detect both IBC and cell-to-cell shorts in submicron DRAMs.

Threshold voltage (Vt) shift was measured, using atomic force probing (AFP) technique, in the pullup PFETs of high density SRAM bitcell arrays in 90nm CMOS bulk technology. This shift caused catastrophic yield loss. The direct measurements of dopant distribution both in plan view and x-section using Scanning Capacitance Microscopy (SCM) technique suggested counter doping of the P-poly had occurred. A single mask modification was shown to validate the observation and eliminated the counter doping resulting in drastic yield enhancement to about 60% from nearly no yield.

The temperature dependence of photocurrent of polycrystalline Si (poly-Si) thin-film solar cells on glass with interdigitated mesa structure has been locally investigated using Infrared Light Beam Induced Current (IR-LBIC) in the temperature range of -25 to +70 °C. The temperature dependence of electrical characteristics of poly-Si thin-film solar cells in reverse bias has been also analysed and compared with the monocrystalline thin-film solar cells. The poly-Si solar cell shows a temperature coefficient (TC) for the photocurrent of around +0.8 and +0.6 %/°C in the grain interior and grain boundary, respectively. The activation energy of the reverse current and also the photocurrent due to the IR laser stimulation has been evaluated, which provide information about traps and their energy levels in the absorber layer of the poly-Si thin-film solar cell. The obtained average value of the activation energy associated with the photocurrent of the poly-Si cell suggests the existence of a shallow acceptor level at around 0.045 eV in the grain boundary and 0.062 eV in the grain interior of the absorber layer of the poly-Si thin-film solar cell. The activation energies of the reverse current for poly-Si and monocrystalline cells have been calculated when the device is biased at -1 and -2 V and the results compared with the activation energy of the saturation current obtained from extrapolation of the I-V curve in the SRH (Shockley-Read-Hall) regime. The results show strong voltage dependence. In both cases the activation energy of the reverse current decreases in the reverse bias voltage, approaching the values obtained from the photocurrent.

The carrier collection properties of polycrystalline Si (poly-Si) thin film solar cells on glass with interdigitated mesa structure have been locally analysed with Infrared Light Beam Induced Current (IR-LBIC) and compared to LBIC measurements using visible light. The low absorption of IR light leads to a low current level when the light is coupled vertically into the active volume. An enhanced carrier collection has been detected at the corners of the mesa because the etch allows to couple the light horizontally into the solar cell, This investigation shows that IR-LBIC is sensitive to light trapping structures in silicon based thin film solar cells.

As the feature size of semiconductor technology shrinks, cross-section metrology becomes more and more challenging. The generation of cross section metrology data is important for the introduction of new advanced integration schemes, rapid yield learning, and continuous process control for stable manufacturing. In this paper an automated way of TEM cross-section preparation by FIB is described to ensure fast cycle time for preparation and analysis. A dual column FIB/SEM system is used to prepare TEM samples from multiple locations of a 300 mm wafer batch. Subsequently, the TEM lamella is transferred to a grid using an ex-situ lift-out station. Two dedicated applications are shown, a Focus Exposure Matrix (FEM) on patterned photo resist and a process control case study on an etched poly-silicon transistor gate.

As a promising candidate for DRAM scaling beyond 40nm technology, the fin cell transistor (FCT) utilizing p-type poly silicon gate (PPG) was proposed. However FCT makes a lot of bridge failure between word-line and landing-plug poly (LPP) connecting source and drain regions in a cell transistor. But this bridge point is so insignificant that the failure was hardly detected by existing read modify write (RMW) pattern. We analyzed this failure with a particular test method. It mostly has been observed to single and odd parity address. We found out that when adjacent gate is active for reading its cell, only the forward bias can run into the LPP with n-type poly-silicon, and low status data would be taken high level turn unlike recess cell array transistor utilizing n-type poly silicon gate (RCAT-NPG) which both high and low status would be reversed.