The results presented here show how high-speed simultaneous EBSD and EDS can be used to characterize the essential microstructural parameters in SnPb solder joints with high resolution and precision. Analyses of both intact and failed solder joints have been carried out. Regions of strain localization that are not apparent from the Sn and Pb phase distribution are identified in the intact bond, providing key insights into the mechanism of potential bond failure. In addition, EBSD provides a wealth of quantitative detail such as the relationship between parent Sn grain orientations and Pb coarsening, the morphology and distribution of IMCs on a sub-micron scale and accurate grain size information for all phases within the joint. Such analyses enable a better understanding of the microstructural developments leading up to failure, opening up the possibility of improved accelerated thermal cycling (ATC) testing and better quality control.

Presence of foreign materials (i.e, contamination) can affect the reliability of copper (Cu) bumps when it affects the wettability of the solder and consequently weakens the joint formation of the copper to the substrate. This paper looks at a case of non-wetting of Cu bumps due to silicon contamination induced during assembly processing. In this case study, surface roughness is the main factor being altered when foreign materials contaminate the metal substrate. Sample devices were tested in a resistive open unit and a direct current failing unit, respectively. It was found that the silicon dust present on the substrate in effect "roughens" the surface, thereby decreasing the wettability between the molten solder to the metal substrate. For future studies, it is recommended that the effect of reliability stress activities on the Cu bumps with silicon contaminations be examined to evaluate the risks for possible field failures of this defect.

An advanced method for LF (Lead Free) bump sample preparation to improve the surface of sample that can enhance the image of IMC (Inter Metallic Compound), solder grain boundary and micro-crack after TC (thermal cycle) reliability test is proposed. By this advanced method application, LF bump micro-crack location and propagation path can be observed easily for the reliability test fracture failure mechanism study and LF bump crack improvement further.

Failures in printed circuit boards account for a significant percentage of field returns in electronic products and systems. Conductive filament formation is an electrochemical process that requires the transport of a metal through or across a nonmetallic medium under the influence of an applied electric field. With the advent of lead-free initiatives, boards are being exposed to higher temperatures during lead-free solder processing. This can weaken the glass-fiber bonding, thus enhancing conductive filament formation. The effect of the inclusion of halogen-free flame retardants on conductive filament formation in printed circuit boards is also not completely understood. Previous studies, along with analysis and examinations conducted on printed circuit boards with failure sites that were due to conductive filament formation, have shown that the conductive path is typically formed along the delaminated fiber glass and epoxy resin interfaces. This paper is a result of a year-long study on the effects of reflow temperatures, halogen-free flame retardants, glass reinforcement weave style, and conductor spacing on times to failure due to conductive filament formation.

While considerable amount of researches and investigations have been made on lead-free solder joint reliability, limited number of literatures are available on the effect of gold content on lead-free solder joint performance. The challenges of lead-free solder/gold metallization interdiffusion during high temperature application/test are: gold embrittlement, intermetallics growth, void formation, and tin-whisker formation. Tin whiskers causing system failures in earth and space-based applications have been reported. This paper illustrates a few case histories of such challenges. The results confirmed that the synergistic effects of void formation, intermetallic compounds formation due to the thick gold plating, and coefficient of thermal expansion mismatch between organic and ceramic substrates resulted in brittle fracture of the solder joint. The tin whisker formation was attributed to the compressive stress in the tin solder material, which was caused by diffusion of the end-cap metallization, formation of intermetallics, and thermal cycling of the soldered components.

The bump nodule growing in electroplating process could be large enough to induce bump to bump short even if the nodule would be weaken by re-flow process. In this work, the microstructure of PbSn eutectic bump and Au bump nodules was analyzed with FIB, SEM and EDS. In PbSn eutectic bump nodule, void defects can be observed with FIB imaging. In Au bump nodule, radiation-like grain structure around the center of Silicon-contained particle can be observed. Based on those analysis results, voids and particles are the source of bump nodule growth. The reason for bump nodule formation is that particles, voids and cathode morphology defects change the roughness of cathode surface, which induces a higher current density area and accelerate local electrocrystallization. Generally, particles, voids and cathode morphology defects are caused by poor photolithography process, tank corrosion and anode contamination such as passivation membrane. Therefore, three conclusions are proposed in this work: 1) where and when the nodules grow can be identified according to their microstructures; 2) cleaning tank and anode periodically can effectively prevent the bump nodules; 3) Qualified photo resist (PR) coating and PR opening process are essential to prevent bump nodule defects.

Printed Circuit Board (PCB) assemblies are moving toward lead-free (LF) alloys and away from the traditional Sn-Pb alloy [1]. This change is creating new and unique failure modes as the process adapts to accommodate the higher temperatures of the new process [2]. In addition, mis-processed lots are more likely due to the complexity of assembling a mix of Sn-Pb and leadfree solders, components, PCBs, solder pastes, and fluxes. This case study helps to highlight the challenge and provides an example of what can happen, how to detect it, and how the defects can cause reliability failures.

During the last few years the drop test has become more and more important for electronic handheld components. Drop test reliability for lead-free solder interconnects is an extreme challenge today. Thus, the need for improved micro structural diagnostics of new material combinations and crack detection methods has increased. The target of this paper is to summarize detection and analysis methods for solder joint cracks, material characterization [1] and preparation methods of assembled printed circuit boards (PCB) after a drop test to completely understand lead-free solder interconnect reliability in fine pitch ball grid array packages (FBGA). In particular, we will introduce the outstanding advantages of embedded cross-sections combined with ion beam polishing (IBP), dye- or rather resin-penetration, selective tin etch and micro-hardness measurements.

Printed circuit board assembly with lead free solder is now a reality for most global electronics manufacturers. Extensive research and development has been conducted to bring lead free assembly processes to a demonstrated proficiency. Failure analysis has been an integral part of this effort and will continue to be needed to solve problems in volume production. Many failure analysis techniques can be directly applied to study lead free solder interconnects, while others may require some modification in order to provide adequate analysis results. In this paper, several of the most commonly applied techniques for solder joint failure analysis will be reviewed, including visual inspection, x-ray radiography, mechanical strength testing, dye & pry, metallography, and microscopy/photomicrography, comparing their application to lead bearing and lead free solder interconnects. Common failure modes and mechanisms will be described with examples specific to lead free solders, following PCB assembly as well as after accelerated reliability tests.

The temperature and strain rate effects on the shear properties of selected Pb-free solders were investigated. The experiments were performed using single lap shear specimens. All testing was performed using a standard tensile test metrology. The following results were found: 1) Sn-3.5 wt.% Ag outperformed all the other solders in terms of its mechanical strength at all test conditions due to the formation of Ag3Sn precipitates in the bulk solder and Cu6Sn5 intermetallic formation along the interface. However, ductility was sacrificed as this solder strain hardens. 2) The strength and ductility of the solder joint is strongly dependent on the test temperature and strain rate. Data in this work reflects a decrease in strength and ductility when the test temperature is increased. This phenomenon can be attributed to the increase in energy as temperature is increased to overcome dislocation barriers such as impurities and grain boundaries that impede the motion of dislocation. When strain rate is increased, the amount of plastic deformation experienced by the solder increases and more dislocations are formed. Due to the increase in proximity and number of the dislocations, the net result is that motion of the dislocations are hindered thus requiring more stress to deform the material.

The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.

The effect of interfacial reaction of Ti/Ni(V)/Au under-bump metallisation (UBM) systems in Pb free solder had been investigated. The objective was to examine the microstructure change and intermetallic formation of Ni-based UBM during isothermal annealing in lead free solder as well as to understand its impact on the UBM failure mechanism. Studies revealed that after IR reflow, spalling of Ni-Sn compound from the UBM took place. A layer of Ni-Sn-V was found to have form in the UBM. The formation of Ni-Sn-V layer was believed to have an impact on the failure mechanism of the Pb free solder. Studies also showed that doubling the Ni layer thickness in this UBM system did not have significant improvement to the overall integrity of the solder joint. However, samples with electroless Ni(P)/Au UBM in lead free solder showed relatively good thermal properties. No major change in the intermetallic composition was observed. More details on the microstructure change during thermal aging of the UBM systems were presented in this article.

In this study, the interface reactions between eutectic SnPb solder and two Ni-based UBM systems are reported, namely the sputtered Cu/Ni(V)/Al and the electroless Au/Ni(P) systems. Comparisons are made to the conventional Au/Al ball bonding system in terms of microstructure evolution, and metallurgical stability. TEM sample preparation is critical in this analysis. The capability of TEM in UBM microstructure studies is demonstrated.

The presence of gold within a Sn/Pb solder joint accelerates diffusion between the Sn and Ni of the Ni- V/Cu underlying bump metallurgy (UBM), generating early failures. A concentration of 1.2 wt% gold in the solder joint can accelerate time to failure by a factor of 400 [3]. The EDS x-ray microanalysis detection limit for gold in tin / lead solder of about 1.2 wt% gold was found to be above the concentration range of interest (0.1 – 0.5 wt% gold). Due to the reliability impact that even a low concentration of gold can have on solder joints employing Ni-V/Cu UBM, a method using differential scanning calorimetry (DSC) was developed to accurately measure gold concentrations of less than 1 wt% in solder bumps.

High temperature gold/tin eutectic (80 Au/ 20 Sn) solder is used in manufacturing for multiple reasons. These motives may include the ability to post solder a part/device without reflow, high temperature field applications, and allow soldering to thick Au layers without the possibility of precipitating AuSn4 brittle intermetallics. In the following military case, Au/Sn eutectic was employed because of high temperature service and the guarantee of no occurrence of gold embrittlement when soldering to the thick Au outer plating. The Au was plated over an electroplated nickel (Ni) layer on a Kovar (iron/nickel/cobalt) housing. The soldering resulted in an extremely poor bond strength of a duroid circuit to the Kovar housing. The results showed contamination in the supplier’s electroplated Ni bath caused the plating to have poor bond strength. The failure occurred within the Ni plating layer.

We investigated the cause of the whisker/discoloration which were found in the transistor lead of stocks (package type TO-18, low power use). In process of the investigation, we estimate two corrosion models that the first model is the remnant of sulfuric acid in cracks of the nickel-phosphorus plating layer in the transistor lead, the second model is the out-gassing or the dissolved ions from the stock container and conductive mat. As the results of the investigation which includes analyses of the whisker/discoloration cross section made by FIB (Focused Ion Beam), a reproductive experiment and so on, the whisker/discoloration were the corrosion reacted between the solder (Pb-Sn) on the transistor lead and SO 4 2- ions of the stock container. We estimate that the new corrosion will not occur and grow in mounted devices because of rejecting the source of corrosion (stock containers). Further, in the worst case of the corrosion occurrence, protective coatings were applied to the mounted transistor lead, as the measure against falling away from the transistor lead.

Mechanical strength, integrity, and reliability of solder connections used in the microelectronics industry are important factors in overall quality and reliability of the finished product. In most cases tin (Sn) rich solders are attached to a base metal plated with nickel (Ni) and then with gold (Au). Formation of AuSn4 intermetallics in the solder may result in loss of more than 80% of the initial impact toughness, resulting in loss of reliability of the connection. Gold (Au) embrittlement is a major concern in tin/lead (Sn/Pb) soldering or any other joining process with Au and Sn as major constituents. Noncompliance to Au plating-thickness specifications by vendors or insufficient Sn wicking of Au surfaces can result in embrittled joints and unreliable parts.

Very highly purified water such as De-ionized (DI) water tends to become very corrosive once exposed to the atmosphere. This “Hungry Water” as known in the water purification world is known to be a major source of corrosion [1]. The DI water was responsible for corrosion of tin during autoclave (pressure cooker) testing of Integrated Circuit (IC) devices assembled in plastic Quad Flat Package (QFP) with fine pitch leads. The copper leads of these packages are plated with solder. The copper leads of the packages are plated with solder composed of Lead and Tin. Due to the effect of corrosive water, Tin from solder corroded during the autoclave testing and formed thin whiskers of solder. These whiskers created a leakage path between the leads causing the devices to fail for pin to pin leakage.

There are three basic methods used to detect voiding and delamination of die attach materials in semiconductor devices. (1)Electrical measurement of a temperature sensitive parameter (e.g. V be , V gs ) under pulsed power conditions is preferred by manufacturers because the data is easily and quickly obtainable during final electrical test; but electrical measurements are only sensitive to gross voiding or delamination. (2)X-ray analysis produces images which are generally accepted as proof of voiding; but X-ray is completely insensitive to delamination or degradation from thermal stress. (3)Use of Scanning Acoustic Microscopy (SAM) as a non-intrusive analysis tool is increasing in the semiconductor industry and provides accurate evidence of delamination in cases where the other two methods fail. The use of all three methods is recommended to maintain a reliable power product fabrication line at its peak of quality with respect to die attach coverage. This paper will compare and contrast the three methods during thermal shock stress in two manufacturer's power Insulated Gate Bipolar Transistor (IGBT) using a lead-tin solder die attach material.