Insulated Gate Bipolar Transistors (IGBT) and silicon carbide (SiC) based MOSFETs have become the predominantly used power semiconductors in particular in automotive applications. For failure analysis of such devices, site-specific access to subsurface fault sites is required, as is understanding their construction and junction profiles, and how the device turns on. We have applied focused ion beam-scanning electron microscopy (FIB-SEM) tomography to visualize inner structure and dopant distributions of an IGBT and of a SiC MOSFET in three dimensions (3D). Such 3D data can be used to complement 2D electron beam induced current (EBIC) measurements obtained at site-specific FIB cross-sections in these devices.

Power devices are now ubiquitous and integral in control of systems across various sectors of the economy. Silicon-based power devices still dominate in most of the applications although new materials and device architectures are becoming common in the next generation of devices. While several techniques to characterize the overall device properties are necessary, the fundamentals in several of these power devices such as Insulated Gate Bipolar Transistors (IGBTs) still rely on healthy junctions for optimal device performance. The technique of Electron Beam Induced Current (EBIC) is used to examine the depletion zones of the p/n junctions between drift and body regions of the device. Simple sample preparation methods such as cleaving the device allows quick cross-section evaluation of the device structure and electrical characterization using EBIC yields good data. The role of acceleration potential on depletion zone thickness is considered during the analysis of intact die and cross-sections. While low voltage EBIC provides images of the p/n junctions in cross-sections, it is found that high voltage (30 kV) EBIC images can also be used to image these same p/n junctions and therefore may point to a very quick line monitor or means for early failure analysis of these devices.

There are three basic methods used to detect voiding and delamination of die attach materials in semiconductor devices. (1)Electrical measurement of a temperature sensitive parameter (e.g. V be , V gs ) under pulsed power conditions is preferred by manufacturers because the data is easily and quickly obtainable during final electrical test; but electrical measurements are only sensitive to gross voiding or delamination. (2)X-ray analysis produces images which are generally accepted as proof of voiding; but X-ray is completely insensitive to delamination or degradation from thermal stress. (3)Use of Scanning Acoustic Microscopy (SAM) as a non-intrusive analysis tool is increasing in the semiconductor industry and provides accurate evidence of delamination in cases where the other two methods fail. The use of all three methods is recommended to maintain a reliable power product fabrication line at its peak of quality with respect to die attach coverage. This paper will compare and contrast the three methods during thermal shock stress in two manufacturer's power Insulated Gate Bipolar Transistor (IGBT) using a lead-tin solder die attach material.