Power MOSFETs are electronic devices that are commonly used as switches or amplifiers in power electronics applications such as motor control, audio amplifiers, power supplies and illumination systems. During the fabrication process, impurities such as copper can become incorporated into the device structure, giving rise to defects in crystal lattice and creating localized areas of high resistance or conductivity. In this work we present a multiscale and multimodal correlative microscopy workflow for the characterization of copper inclusions found in the epitaxial layer in power MOSFETs combining Light Microscopy (LM), non-destructive 3D X-ray Microscopy (XRM), Focused-Ion Beam Scanning Electron Microscopy (FIB-SEM) tomography coupled with Energy Dispersive X-ray Spectroscopy (EDX), and Transmission Electron Microscopy (TEM) coupled with Electron Energy Loss Spectroscopy (EELS). Thanks to this approach of correlating 2D and 3D morphological insights with chemical information, a comprehensive and multiscale understanding of copper segregations distribution and effects at the structural level of the power MOSFETs can be achieved.

The development of modern power semiconductors requires the reduction of the resistance in the on-state of the device. One way to accomplish this is to reduce the bulk silicon thickness. To reach low final Si thicknesses, the grinding processes have to be adapted and optimized and new process-flows, such as dicing before grinding (DBG), must be employed.

Government regulations focused on reducing carbon footprint are driving the widespread adoption of cleaner and more energy-efficient electric vehicles (EV/HEV). As electric vehicles continue to be adopted widely, the power electronics market has experienced tremendous growth. To achieve better thermal, electrical, and lifetime reliability, novel processes and advanced materials are frequently assessed, incorporating high temperature/pressure conditions. Given the high safety requirements for vehicles, a reliable power electronics construction is critical. The generic trend in power electronics prompts the evaluation of a robust non-destructive failure analysis technique at the component-level. Scanning acoustic tomography (SAT) stands out as one of the most effective nondestructive tools for conducting failure analysis of the semiconductors. This technique proves valuable for visualizing defect characteristics, including their morphology, location, and size distribution prior to any destructive physical testing. Furthermore, SAT also exhibits a remarkable capability to detect delamination at sub-micron levels. In this paper, one of the most prominent methods of SAT, the “Tomographic Acoustic Micro Imaging” (TAMI) is capable to inspect the sample subsurface layer by layer simultaneously with an excellent penetration of the ultrasonic waves while scanning the material surface. The objective of current work is to detect the defect and localize the defect, nondestructively. The choice of methodologies, such as the structure of device under test, transducer selection and gate setting will be elaborated further in further sections.

Threading dislocations are a feature of all current GaN-based power devices and are speculated to impact their performance and reliability. The aim of this study is to cross-correlate electrical and physical characterization of dislocations using electron beam induced current (EBIC), electron channeling contrast imaging (ECCI), and transmission electron microscopy (TEM) analysis techniques. Sample preparation steps such as deposition and etching of markers via focused electron beam (FEB) and focused ion beam (FIB) turned out to be decisive for successful characterization. We describe in detail various approaches required for successful cross-correlation and present appropriate workflows.

Insulated Gate Bipolar Transistors (IGBT) and silicon carbide (SiC) based MOSFETs have become the predominantly used power semiconductors in particular in automotive applications. For failure analysis of such devices, site-specific access to subsurface fault sites is required, as is understanding their construction and junction profiles, and how the device turns on. We have applied focused ion beam-scanning electron microscopy (FIB-SEM) tomography to visualize inner structure and dopant distributions of an IGBT and of a SiC MOSFET in three dimensions (3D). Such 3D data can be used to complement 2D electron beam induced current (EBIC) measurements obtained at site-specific FIB cross-sections in these devices.

Atom probe tomography is used to characterize the 3D Al dopant distribution within the gate diffusion region of a deconstructed SiC n-channel junction field effect transistor. The data reveals extensive inhomogeneities in the dopant distribution, which manifests as large Al clusters - some of which are ring-shaped and indicative of dopant segregation to lattice defects in the SiC. The presence of defects in the SiC is confirmed by transmission electron microscopy of an identical region. Factors that may impact the atom probe data quality and consequently complicate data interpretation are considered, and their severity evaluated. The possible origin of the lattice defects in the SiC and the corresponding implications for device performance and reliability are also discussed. Overall, the utility of atom probe tomography and correlative transmission electron microscopy for revealing potential failure mechanisms of next-generation semiconductor devices is demonstrated.

A commercially available 4H-SiC power device and a GaN on SiC HEMT were examined with Ga-FIB sectioning and various junction analysis techniques. The impact of Ga-FIB on the electronic properties of such power devices is observed to be less significant than anticipated. A field of view was FIB-milled into the structure, exposing a row of devices. In this window, p/n junctions were evaluated by Passive Voltage Contrast (PVC), Electron Beam Induced Current (EBIC), and Kelvin Force Probe Microscopy (KFPM). Results showed excellent fidelity to expectations and each technique brought out new insights. In further work, the gate voltage was varied and the changing of depletion zones upon device turn-on was observed. This work: 1) Demonstrates complete sufficiency of Ga-FIB cross sections for regular cross-sectional work. 2) Demonstrates a novel method for investigating junction properties from Ga-FIB sections of power devices which largely leaves the rest of the device intact. 3) Provides some assurance that the Ga-FIB does not severely impact the evaluation of junction properties in some power semiconductors. 4) Points to alternative mechanism for device turn-on.

Power devices technology and in particular devices based on 4H-SiC require a thick metal layer in top to make a source contact and on the backside to make a drain contact. These metal layers are the main problem for fault isolation activities. Up today, many fault isolation techniques do not allow for results, and it is mandatory to remove this layer before performing them. During the metal removal on wafer there is a high probability of damaging the sample or breaking the wafer, especially if the latter is very thin. In this analysis we show a methodology that allows fault isolation analysis, performed on wafers with metal layers, preventing the risks of sample damage induced from preparation.

Presentation slides for the ISTFA 2023 Tutorial session “Power Semiconductor Failure Analysis Tutorial.”

Presentation slides for the ISTFA 2023 Tutorial session “Reliability and Failure Analysis of SiC Power Devices and Modules.”

Power devices are now ubiquitous and integral in control of systems across various sectors of the economy. Silicon-based power devices still dominate in most of the applications although new materials and device architectures are becoming common in the next generation of devices. While several techniques to characterize the overall device properties are necessary, the fundamentals in several of these power devices such as Insulated Gate Bipolar Transistors (IGBTs) still rely on healthy junctions for optimal device performance. The technique of Electron Beam Induced Current (EBIC) is used to examine the depletion zones of the p/n junctions between drift and body regions of the device. Simple sample preparation methods such as cleaving the device allows quick cross-section evaluation of the device structure and electrical characterization using EBIC yields good data. The role of acceleration potential on depletion zone thickness is considered during the analysis of intact die and cross-sections. While low voltage EBIC provides images of the p/n junctions in cross-sections, it is found that high voltage (30 kV) EBIC images can also be used to image these same p/n junctions and therefore may point to a very quick line monitor or means for early failure analysis of these devices.

In this work we have investigated the results obtained using fault isolation techniques such as EMMI, OBIRCH and OBIC on a Wide band gap power device and in particular a 4H-SiC. We used YLF laser and Green Laser and showed the differences in the resulting hot spots. In the selected point, FIB cross sectioning and EDS analysis was performed. Once that the defect was shown, the differences the fault isolation results were discussed.

This paper discusses the steps involved in the failure analysis of power semiconductor devices in which leakage currents are observed and can be traced to doping-profile variations in ion-implanted layers. The discovery and assessment of such defects takes knowledge and skill in sample preparation, fault isolation, and the use of advanced inspection techniques, particularly scanning capacitance microscopy, as explained in the paper. Several diodes, MOSFETs, and IGBTs were examined using the proposed approach and the results are presented along with SCM images showing incomplete and poorly shaped ion-implanted structures determined to be the root cause of failure in each case.

This presentation demonstrates how Time-of-Flight Secondary Ion Mass Spectroscopy provides unique information to identify suspect counterfeit semiconductor devices. An example is shown where the epitaxial layers of a light emitting device (LED) do not match those of the exemplar. Keywords: Secondary Ion Mass Spectroscopy, SIMS, counterfeit detection, LED, Light emitting diode.

High core-Vdd overvoltage latchup margins in CMOS ICs are required to enable many reliability screens (e.g., DVS and HTOL testing). We introduce an efficient way to isolate defects that degrade these margins using PEM and 1064/1340 nm CW laser-stimulation. Current pulses from a current amplifier are used to rapidly charge and discharge the DUT power rail to repetitively ramp Vdd to (or near) the latchup threshold. The characteristic drop in Vdd when latchup is induced is used to generate a latchup flag for laser-stimulation mapping. Latchup events are automatically terminated and latchup durations are minimized, leading to high stability/repeatability of the technique. Isolations down to the cell level were successfully performed in sub-14 nm FinFET test vehicles. This level of isolation is unmatched and this is the first reported use of thermal laser stimulation for latchup investigations. In one provided example, the latchup trigger was isolated to FET based decoupling capacitors (decaps) widely used as fill.

In this paper, the stacking fault defects in FinFETs are described as the root cause of the PLL failure. Failure analysis approaches such as photon emission microscopy and nano probing were applied to pinpoint the exact stacking fault location in even transistor level and High resolution TEM confirmed the stacking fault defects in the Fin which was isolated by nano probing. RX local density was confirmed as the key factor in stacking fault generation by TCAD simulation. RX new mask with dummy addition was made to mitigate stress and was confirmed to be effective to reduce the compressive strain at the channel in FinFETs by Geometric Phase Analysis (GPA) which provided sufficiently practical local strain measurement data. The GPA techniques demonstrated here are informative for process improvement and failure analysis in FinFET devices. Keywords – Stacking Fault, Geometric Phase Analysis

This paper describes an electrical and physical failure analysis methodology leading to a unique defect called residual EG oxide (shortened to REGO); which manifested in 14nm SOI high performance FinFET technology. Theoretically a REGO defect can be present anywhere and on any multiple Fin transistor, or any type of device (low Vt, Regular Vt or High Vt). Because of the quantum nature of the FinFET and REGO occurrence being primarily limited to single Fins, this defect does not impact large transistors with multiple FINs; moreover, REGO was found to only impact 3 Fin or less transistors. Since REGO can be present on any multi-FIN transistor the potential does exist for the defect to escape test screening. Subsequently a reliability BTI (Bias Temperature Instability) stress experiment by nanoprobing at contact level was designed to assess REGO’s potential reliability impact. The BTI stress results indicate that the REGO defect would not result in any additional reliability or performance degradation beyond model expectations.

An application-specific integrated circuit (ASIC) for a high reliability application is found to have a missing sidewall spacer in a single transistor. Manufacturer burn-in and standard component electrical tests do not capture this defect. The defect manifests after exposure to ionizing radiation. Photon emission microscopy (PEM), laser voltage imaging (LVI), and laserassisted device alteration (LADA) are used to isolate the failure site. At the failure site a focused ion beam (FIB) cross section indicates that a doubly doped drain (DDD) (N+) is likely present where a lightly doped drain (LDD) is designated. This defect leads to a failure mode that is consistent with hot-carrier injection in complementary metal-oxide semiconductor (CMOS) transistors. This paper presents the testability from a fault isolation aspect, shmoo plot characterization, and backside optical techniques to identify its spatial location. A discussion of the results includes why ionizing radiation allowed the defect’s capture and potential implications of using ionizing radiation as a viable failure analysis technique.

Root cause analysis of parametric failures in mixed-signal IC designs has been a challenging topic due to the marginality of failure modes. This work presents two case studies of offset voltage (Vos) failures which are commonly seen in mixed-signal IC designs. Nanoprobing combined with Cadence simulation becomes a powerful methodology in fault isolation. Large Vos is typically caused by the mismatch of electrical properties of the components on two balanced rails. In our first case, we present a case-study of nanoprobing combined with bench test and Cadence simulation to debug the root cause of a class-D amplifier voltage offset related yield loss from mixedsignal design sensitivity. Bench electrical measurements confirm the dependency of offset voltage (Vos) on boost voltage (VBST) and amplifier gain settings, which isolates the root cause from mismatch in amplifier gain resistors. The bench measurements match extremely well when an extra parasitic resistance is added to the input of the amplifier in the Cadence simulation. Kelvin 4 points nanoprobing on the amplifier input matching resistors confirmed a 40% mismatch as a result of both layout sensitivity and fabrication. This case highlights that the role of nanoprobing combined with Cadence simulation is not only valuable in physical failure root cause analysis but also in providing guidance to a potential process fix for current and future designs. In our second case, a decrease in offset voltage (Vos) is found through bench validation by reducing the supply voltage (VDD), suggesting a new mismatch mechanism related to the body-source bias. Nanoprobing of the input PMOS transistors clearly shows humps in the subthreshold region of IV characteristics, and the severity of humps increases with body-source bias. Vos derived from the nanoprobing results aligns well with the bench data, suggesting hump effect to be the root cause of Vos deviation. This study suggests that by combining Cadence simulation and nanoprobing in the failure analysis process of parametric failures, suspicious problematic devices can be identified more easily, greatly reducing the need for trial and error.

This paper demonstrates a two-pin Electron Beam Induced Current (EBIC) isolation technique to isolate the defective Fin with gate oxide damage in advanced Fin Field Effect Transistor (FinFET) devices. The basic principle of this twopin configuration is similar to two-point Electron Beam Absorption Current (EBAC) technique: a second pin as ground on the gate is added to partially shunt the EBIC current and thus creates EBIC contrast from the defective Fin. In this way, the challenge of highly resistive short path inside the Fin in a narrow gate can be overcome. The paper will provide failure analysis details using this technique for defective Fin isolation.