Presentation slides for the ISTFA 2024 Tutorial session “Failure Analysis Challenges for Chip Scale Packages (2024 Update).”

Presentation slides for the ISTFA 2024 Tutorial session “Fundamentals and Emerging Capabilities: 3D X-Ray Imaging for Semiconductor Advanced Package Failure Analysis.”

Digital fault localization for semiconductor devices failing Automatic Test Pattern Generation (ATPG) tests can be a very challenging task, particularly when the package of the device does not lend itself towards dynamic stimulation techniques. In the case of wire-bonded Ball-Grid-Array (BGA) devices, complete electrical functionality may only be preserved when access to the die is done from the frontside of the unit. This imposes significant limitations to the applicable optical fault isolation (OFI) techniques and their resolution in highlighting an anomaly, especially in advanced technology nodes that incorporate several metal layers. This paper explores the use of digital VDDLV supply domains as a means of activating defects inside specific logic areas, as an alternative to complex electrical setups, thus overcoming the package related limitations.

Advanced packaging of electronic components is increasing complexity of single packages containing up to hundreds of individual components in a 3-dimensional arrangement. X-ray nano-tomography enables to resolve these complex structures in 3D with sub-micron resolution for failure analysis. Here we present a study using a cutout from an embedded multi-die interconnect bridge (EMIB) scanned with a custom nano-CT system utilizing a state-of-the-art nano focus X-ray source. For comparison, a scan using a commercial electronics imaging system was performed as well. We demonstrate that micron and sub-micron sized defects can be identified enabling failure analysis on the sub-micron level.

This paper describes the detailed sample preparation of direct Cu-to-Cu bonding in 3D packaging between processor and memory. Different sample preparation techniques are described and compared. The sample preparation methods will then be confirmed by advanced structural characterization and strain measurement. The presence of voids and strain at the bonding interface is associated with the development of device failure.

This paper presents a novel method for determining the Z-depth location of short circuit defects in flip chip packages using lock-in thermography (LIT). The approach analyzes phase shift values from localized hot spots using the LIT system's "Image Statistics" feature, specifically focusing on phase "mean" values at specific lock-in frequencies. Through extensive testing on 2.5D stacked silicon interconnect technology (SSIT) packages exhibiting short failures, we established a strong correlation between phase mean values and the vertical location of defects. This technique's reliability was validated through both physical analysis and non-destructive verification methods, demonstrating its effectiveness as a precise diagnostic tool for complex semiconductor packages.

In the field of semiconductor failure analysis, new sample preparation challenges arise due to the emergence of new chip architectures, such as 3D Back Side Imager (BSI) products. Indeed, these products are constituted of a specific stack: an imager chip at the top associated back-to-back with a digital chip at the bottom on a silicon substrate carrier. All the work presented hereafter is triggered by a nano-probing analysis case on a failing pixel of the imager chip. The analysis consists in characterizing the transistors of the pixel at contact level to isolate the electrical failure. It imposes to keep the integrity of the top chip (imager chip) front-end layers to have the possibility to measure the transistors. It can only be achieved by de-processing from the silicon substrate carrier side. Thus, the particularity of the 3D BSI chip conception implies a more complex delayering protocol than the ones commonly used. In this paper, the sample preparation protocol is presented in detail and its successful implementation is demonstrated through a concrete analysis case in 3D BSI 40 nm technology. This paper also discusses the advantages of the technical solutions implemented to overcome the complexity of the presented architecture.

This paper discusses the application of the RF-LIT technique to a variety of use cases. The technique itself was introduced during last year’s ISTFA 2023 conference. The present work aims to showcase its suitability for the analysis of polyline cracks and packaging related fails such as via opens in RDL as well as cracks in solder joints. Further, a model is constructed explaining why RF-LIT can work and where the frequency dependence comes from.

Over the past decade, the semiconductor industry has increasingly focused on packaging innovations to improve device performance, power efficiency, and reduce manufacturing cost. The recent heterogeneous integration offers an attractive solution in advanced IC packaging because it enables the integration of diverse functional components, such as logic, memory, power modulator, sensor on a single package platform. However, the adoption of the emerging structures, materials and components in advanced packages has challenged the existing fault isolation and analysis techniques. One of the major challenges is the limited accessibility to defects because fault regions are often located deep within devices. Without high-accuracy positional information of a defect, physical cross-sectioning and FIB polishing may alter or destroy the evidence of root causes. A non-destructive microscopic approach is preferred to map defective sites and surrounding structures. However, this method is limited by spatial resolution, especially for analyzing novel submicron interconnects such as fine pitch microbumps, redistribution layers (RDLs), and hybrid bonds. In this paper, we report an AI powered correlative microscopic workflow, where non-destructive X-ray imaging, FIB polishing and high-resolution SEM analyzing techniques are combined to solve the accessibility problem. Because 3D X-ray imaging may take a larger fraction of the time span over the entire workflow, a deep-learning based reconstruction method was applied to accelerate data acquisition. Several next-generation packages, fan-out wafer-level package (FOWLP) and hybrid bonds with sub 10 µm pitch, were used as the test vehicles to demonstrate the workflow performance and efficiency.

A system-in-package (SiP) design takes advantage of cutting-edge packaging technology and heterogeneous integration (HI) in response to the growing need for aggressive time-to-market, high-performance, less expensive, and smaller systems. However, aggregating dies with different functionalities introduces new attack vectors with fault-injection attacks (FIA) that can effectively alter a circuit's data and control flow maliciously to cause disruptions of secure communication or sensitive information leakage. Additionally, traditional threat models associated with FIA on a 2D monolithic system-on-chip (SoC), and the corresponding mitigation techniques may not be compatible with modern 2.5D and 3D SiP architectures. To address these limitations, we propose system-aware fault injection attack detection for SiP architectures (SYSFID), a real-time and on-chip sensor-based fault monitoring approach integrated into a system-level design. SYSFID detects any fault-induced anomalous alterations in path delays of the components of inter-chiplet networks by strategically placing on-chip fault-to-time converter (FTC) sensors and controlling them efficiently to safeguard overall system security. To demonstrate the effectiveness of SYSFID, we detect several fault injection attempts on the FPGA implementation of a network-on-chip (NoC) based architecture during secure network packet transfers. Our experiments also illustrate that the SYSFID framework reliably senses both global and local FIAs with minimal overheads.

This paper presents a method for statistical analysis of ball grid array (BGA) pin degradation in packaged devices. A novel testing system is demonstrated featuring parallel monitoring of numerous pins, fast thermal cycling, and precise degradation data generation even in moderate stresses. The resistance change data due to temperature cycling stress is compared to stress on the pin due to its location on the chip. The results are vital for localizing vulnerabilities in pins that are not location-specific in the chip. The methods introduced in this study can be expanded to analyze advanced packaging assemblies.

In advanced chip package failure investigations, Electro Optical Terahertz Pulse Reflectometry (EOTPR) simulation emerges as a highly effective fault isolation technique. However, traditional manual methods for generating simulation models face significant challenges, including laboriousness, time consumption, and susceptibility to human error. To address these obstacles, we have developed an automation software script in-house. This script autonomously interfaces with the design database, extracting crucial trace information and generating an optimized equivalent trace model. This automated process markedly enhances the efficiency of EOTPR model simulations, streamlining workflow, standardizing procedures, and reducing the potential for human error. The efficacy of integrating the automation script into the workflow of advanced package failure analysis was demonstrated through two case studies. This integration significantly enhanced productivity and enabled successful root-cause investigation of advanced package failures.

The rapid development of advanced packaging technologies for high-performance computing (HPC) applications poses significant challenges for sample preparation methodologies. Conventional techniques are often insufficient to cope with the complex architectures and heterogeneous materials of modern packages, such as COWOS (Chip-on-Wafer-on-Substrate) and 3D structures. In this paper, we present a novel approach for sample preparation that leverages precision CNC (Computer Numerical Control) milling and selective MIP plasma etch. These methods enable precise and selective removal of unwanted material, while preserving the integrity of the target region of interest. We demonstrate the effectiveness of our approach on various advanced packages and show how it facilitates the failure analysis tasks for HPC chips.

The semiconductor industry is no longer driven purely by performance. Miniaturization, increased functionality, low latency and high bandwidth requirements are becoming more important. Furthermore, as Moore’s law scaling becomes more difficult and costly, innovations in packaging technologies through heterogeneous integration are being adopted rapidly to meet these demands. This paper discusses how defects in InFO (Integrated Fan-Out) wafer level multi-die semiconductor packages can be successfully root caused and describes the challenges faced when doing failure analysis of such packages.

Board level semiconductor reliability testing (BLTT) is a crucial step in the product development life cycle of modern electronics. While the primary focus of semiconductor reliability historically has been to understand the robustness of the solder joint, there are other aspects of the semiconductor package which are also susceptible to failure after the product has been assembled. Despite its overwhelming importance, there is no one centralized resource outlining best practices for conducting BLRT across industries. Fortunately, industry standards do exist. Among them are outlines for conducting tests including temperature cycling, mechanical shock, humidity dwell among others. In this work we present a case study exploring some of the unique challenges and methods associated with conducting BLRT using mechanical shock testing. Namely, we discuss the practical challenges of conducting these tests in the presence of a constant noise source and performing die level failure analysis on components suffering from warpage while back side films (BSFs) are applied as a protective coating on the package.

We introduce a laser tool for producing cross-sectional and block cuts of cubic millimeter dimensions in advanced packages and other samples. Polaris TM is an alternative to mechanical polishing and can create samples of arbitrary shapes including block cut-outs and window cuts. The tool uses a femtosecond laser for ablation to reduce thermal effects on the sample. To further control the sample temperature, the tool can also cut samples that are submerged in water. We show results cutting in advanced packages with minimal damage at high speed, typically greater than 1 mm 3 /min.

For decades, device scaling has been the primary driver of the performance boost in integrated circuit (IC) devices. However, this trend has slowed down in recent years due to physical limitations and technical challenges. To continue meeting the ever-increasing demand for high-performance computing, other innovations such as advanced transistor designs and packaging schemes have emerged. Advanced transistors, such as FinFETs and Gate-all-around FET (GAAFETs), have been developed to overcome the limitations of traditional planar transistors, offering higher performance and energy efficiency. Meanwhile, advanced packaging schemes, such as system-in-package (SiP), 2.5D, and 3D packaging, offer higher integration densities, improved thermal management, and faster data transmission. These innovations are crucial in driving the development of high-performance computing, and they will play an essential role in meeting the growing demand for faster and more efficient computing.

Antenna-in-packaging (AiP) enables the next generation of high-performance wireless 5G mmWave communication and beyond by incorporating antenna arrays in small form factors using System in Package (SiP) technology. The trend toward heterogeneous integration and advanced packaging will likely introduce more complexity to the semiconductor supply chain. In addition, there is also the risk of becoming more susceptible to security vulnerabilities associated with advanced packaging. This paper provides an overview of the supply chain vulnerabilities in advanced packaging and heterogeneous integration, followed by the existing security, reliability issues, and assurance of AiP. Apart from discussing existing physical modalities of AiP assurance and vulnerabilities, we propose Radio Frequency Fingerprint (RFF) as a new physical modality for AiP assurance. We also discuss possible future research direction and application of RFF in AiP assurance.

Continued advancements in the architecture of 3D packaging have increased the challenges in fault isolation and failure analysis (FA), often requiring complex correlative workflows and multiple inference-based methods before targeted root cause analysis (RCA) can be performed. Furthermore, 3D package components such as through-silicon-vias (TSVs) and micro-bumps require sub-surface structural characterization and metrology to aid in process monitoring and development throughout fabrication and integration. Package road-mapping has also called for increased die stacking with decreased pitch, TSV size, and die thickness, and thus requires increased accuracy and precision of various stateof- the-art analytical techniques in the near future. Physical failure analysis (PFA), process monitoring, and process development will therefore depend on reliable, high-resolution data directly measured at the region of interest (ROI) to meet the complexity and scaling challenges. This paper explores the successful application of plasma-FIB (PFIB)/SEM techniques in 2D and 3D regimes and introduces diagonal serial sectioning at package scales as a novel approach for PFA and metrology. Both 2D and 3D analysis will be demonstrated in a high bandwidth memory (HBM) package case-study which can be applied more broadly in 3D packaging.

In this work we present a new defect localization capability on Wafer Level Chip Scale Packages (WLCSP) with small-scale Cu pillars using advanced 3D X-ray microscopy (XRM). In comparison to conventional microcomputed tomography (Micro-CT or microCT) flat-panel technology, the synchrotron-based optically enhanced 3D X-ray microscopy can detect very small defects with submicron resolutions. Two case studies on actual failures (one from the assembly process and one from reliability testing) will be discussed to demonstrate this powerful defect localization technique. Using the tool has helped speed up the failure analysis (FA) process by locating the defects non-destructively in a matter of hours instead of days or weeks as needed with destructive physical failure analysis.