For advanced node semiconductor process development, manufacturing, fault isolation and product failure analysis, nanoprobing is an indispensable technology. As the process technology node scales, transistors and materials used are more susceptible to electron beam damage and changes. As scanning electron microscope (SEM) energy decreases to minimize electron beam damage, imaging resolution degrades. Process scaling has not only affected patterning dimensions and pitch scaling, but also materials utilized in advanced nodes. The material used at the contact level has changed from tungsten (W) to cobalt (Co), in combination with ultra-low K dielectrics. These new materials tend to make sample preparation and probing increasingly more challenging. At advanced nodes with sub-20nm contacts, probe landing accuracy and probe-contact stability are important to maintain good electrical contact throughout measurement time. In this paper, we discuss nanoprobing results from a 7nm SRAM obtained from a commercially available leading edge 7nm SOC.

Conventional series resistance imaging methods require electrical contacts for current injection or extraction in order to generate lateral current flow in the solar cell. This paper presents a new method to generate lateral current flow in the solar cell without any electrical contacts. This reduces the sample handling complexity for inline application and allows for measurements on unfinished solar cell precursors.

Degradation of contact mating surfaces can produce a wide range of problems including intermittent failures and also full functional failures in all computer systems. This paper discusses the complexity involved with investigating the failure mechanism and root cause for intermittent memory failures on a product from end customers. Also discussed in detail is the approach of fault isolation followed by hypothesis development & physical analysis to arrive at root cause of failure. Fault isolation was achieved through register probing. Three major hypotheses were put forth namely plastic debris, misalignment and contact area issues. The physical analysis data collected through optical inspection, 2D x-ray, cross section and SEM analysis coupled with EDX to prove or disprove the hypotheses, revealed contact area corrosion in the form of nickel oxide. Contributors like gold plating thickness and plating porosity of the mating surfaces was verified to be not an issue in this case. Further analysis on the connector pins, memory modules and the contact area indicated damage to the connector pins leading to nickel exposure. The root cause for damage to the pins was analyzed to be a result of memory modules being inserted at an angle. Further studies are planned to look into design issues of connectors and memory modules to minimize damage to the contact area.

Contrary to known art, we have discovered that lubricated tin-silver connectors have better electrical performance and are more reliable than lubricated silver-silver connectors under high-current and high-vibration conditions. The antifretting lubricant, that enhances the performance and reliability of the tin-silver connectors, is a grease consisting of a hydrocarbon oil in a nano-sized silica-particle base. Focused ion beam and scanning electron microscopy were used to understand the contact degradation mechanism. The superior electrical performance and reliability of the lubricated tin-silver connectors is due to a mechanism that replaces the tin plating from the contact surface with a coating of silver. The removal of the tin plating may be due to wear and the replacement by the silver coating may be due to an electrochemical displacement reaction.

The electrical interface, in terms of a reliable, low ohmic and defined connection with the device or die is the most relevant aspect in the characterization of products. Bad or undefined contacts inhibit an exact assessment of the functionality. This paper describes different contact related failures analyzed in our lab and gives the solutions we used to solve the problems. Especially an electroless (nickel)-gold plating method has been optimized and is described in details. Low ohmic and reliable contacts can be produced; the paper shows several applications to improve the contact quality in different domains of the failure analysis business

For its latest generation of high performance logic applications, Motorola employs a 0.13 µm CMOS technology with shallow trench isolation (STI). The contact dimension and spacing requirements for the dense areas of the circuitry, such as the cache, are quite aggressive. We recently encountered single bit and massive array failures, which were traced to an electrical short between tungsten contacts. We report here the failure analysis, which involved electrical and physical testing techniques.

Focused ion beam (FIB) techniques are continuously improved to meet the demands of shrinking device dimensions and new technologies. We developed a simultaneous milling and deposition FIB technique to provide electrical contact to small buried targets in semiconductors. This method is applied to directly connect the deep trench (DT) capacitor of a DRAM single cell in deep submicron technology. By carefully adjusting the deposition parameters (scanned area < (0.3 µm)2, beam current < 20 pA) we are able to influence diameter, depth and Pt fill properties of the hole to meet the very restricted requirements for successful DT connection (hole diameter < 200 nm at DT level). Electrical measurements are performed on DRAM single cells after connecting buried plate (n-band), p-well, wordline, bitline and DT. The probe pads were Pt, deposited with ion beam assistance, on top of highly insulating SiOx, deposited with electron beam assistance by using a dualbeam FIB. The read and write conditions of an active memory cell are studied. The presented method increases the capabilities to localize and characterize trench related failure mechanisms.

Low-pressure conditions, as experienced in space applications, are considered benign for many electronic components. However, for switching devices the probability of failure may be significantly greater than at normal atmospheric pressure due to arcing-at-break processes. This study was stimulated by a relay failure in a 60-V power bus in a spacecraft module, and it was intended to analyze failure modes and the probability of their occurring under lowpressure conditions. The effects of gas pressure, power bus voltage, and load current on arc duration and probability of arc flashover have been investigated. It was shown that arc duration mostly depends on switching power and gas pressure, significantly increasing when power is rising and pressure is decreasing. Failure analysis indicated two major mechanisms in low-pressure conditions: (1) contact damage (excessive erosion and/or microwelding) and (2) arc flashover to a grounded case and/or grounded coil post. For a relay operating in a vacuum, the effect of leak rate on the time to failure at low-pressure conditions is discussed.