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Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 45-53, November 12–16, 2023,
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Integrated capacitors use metal plates such as in Metal-Insulator-Metal (MIM) and Metal-Oxide-Metal (MOM) capacitors while Polysilicon and Silicon (Si) substrate for metal-oxide-semiconductor (MOS) capacitors. Three major challenges and solutions were discussed in this technical paper. First, the failure site localization of a subtle defect in the capacitor plates. To determine the specific location of the defect site, Electron Beam Induced Current (EBIC) analysis was performed while the part was biased using a nano-probe set-up under Scanning Electron Microscopy (SEM) environment. Second, Failure Mechanism contentions between Electrically Induced Physical Damage (EIPD) or Fabrication process defect particularly, for damage site that is not at the edge of the capacitor and without obvious manifestations of Fabrication process anomalies such as bulging, void, unetched material or shifts in the planarity of the die layers. To further understand the defect site, Scanning Transmission Electron Microscopy (STEM) coupled with Energy-Dispersive X-ray Spectroscopy (EDS) were utilized to obtain high magnification imaging and elemental area mapping. Third, misled conclusion to be an EIPD site manifested by burnt and reflowed metallization. The EIPD site was only a secondary effect of a capacitor dielectric breakdown. This has been uncovered after understanding the circuit connectivity, inspections of the capacitors connected to the EIPD site, fault isolation and further physical failure analysis were performed. As results of the Failure Analysis (FA), Customer and Analog Devices Incorporated (ADI) manufacturing hold lots were accurately dispositioned and related corrective actions were precisely identified and implemented.
Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 324-329, October 31–November 4, 2021,
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Defects associated with metal-insulator-metal (MIM) capacitor failures can be difficult to locate using conventional fault isolation techniques because the capacitors are usually buried within a stack of back-end metal layers. In this paper, the authors explain, step by step, how they determined the cause of MIM capacitor failures, in one case, in an overvoltage protection device, and in another, a high-speed digital isolator circuit. The process begins with a preliminary fault isolation study based on OBIRCH or PEM imaging followed by more detailed analyses involving focused ion beam (FIB) cross-sectioning and delayering, micro- or nano-probing, resistive or voltage contrast imaging, and other such techniques.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 57-60, November 15–19, 2020,
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The paper demonstrates accurate fault isolation information of metal-insulator-metal (MiM) capacitor failures by lock-in thermograph (LIT). In this study, a phase image spot location at a lock-in frequency larger than 5 Hz gives more accurate defect localization than an LIT amplitude image or OBIRCH to determine the next FA steps.
Proceedings Papers
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 508-514, November 9–13, 2014,
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An increasing number of foil capacitors (metallized thin film capacitors, MTFC) are used as filters in power converters. Thus, they are constantly connected between power lines (different phases) or between power lines and ground. However, after some years of operation, severe damage cases were observed, where filter capacitors became extremely hot and started a slow process of outgasing which sometimes is even ended by catastrophic burning. Failure analysis of surviving capacitors of the same kind in neighbor phases identified air inclusions as the cause, which led to internal corona discharge. Useful corona discharge measurements, based on a modification of the well-known partial-discharge (PD) tests, made it possible to assess capacitors on their potential risk of such failures. It turned out that many, even new foil capacitors, started internal corona discharge already underneath their official AC voltage specification.
Proceedings Papers
ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 164-169, November 11–15, 2012,
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This paper presents the memory cell level passive voltage contrast (PVC) involving diode, capacitor and transistor devices in a (dynamic random access) DRAM chip. More particularly, we show that the voltage contrast sensitivity can be improved significantly by the adjustment of scan location and scan location sequence. Both leaky and resistive fault localizations by PVC imaging are presented to illustrate our point.
Proceedings Papers
ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 31-34, November 13–17, 2011,
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For most advanced semiconductor products, Focused Ion Beam (FIB) circuit modification and node access through the backside of the chip is the only viable approach. The high density of interconnect wiring and the presence of C4 solder bumping for chip to module attachment has made complex edits virtually impossible with long standing conventional frontside techniques. Unfortunately, the presence of buried circuit elements on the very latest designs greatly complicates the backside editing formula. The introduction of deep trench capacitors as a distributed circuit element in logic designs has had a profound impact on the established methods of backside FIB chip editing. In many cases wide area preparatory trenching down to the underside of circuitry cannot be done without damage to structures that penetrate the silicon adjacent to active transistors by as much as 10 microns. The decision whether to remove these devices or attempt to work around them requires an analysis of the impact on circuit performance and an assessment of the working space (control of anisotropy of etch, aspect ratio issues, etc.) available for executing the edit. IBM is in the process of developing a new set of procedures for performing FIB backside edits on circuits that incorporate these buried structures.
Proceedings Papers
ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 230-233, November 13–17, 2011,
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This paper focuses on infrared (IR) thermography capabilities on III-V components for thermal measurements applications and failure analysis (FA). The first part discusses the thermal mapping on InGaAs/AlGaAs PHEMT structure and compares IR thermal measurement with the well-known techniques as Raman and SThM. The second part discusses IR thermography on challenging FA for hot spot detection on the most popular type of capacitor for III-V MMICs as the metal-insulator-metal capacitor. It shows how IR thermography can easily localize very small pinholes in SiN, where liquid crystal and OBIRCH techniques are not well adapted.
Proceedings Papers
ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 316-321, November 13–17, 2011,
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Some process abnormalities can be very difficult to detect with conventional FA techniques. Scanning Capacitance Microscopy (SCM) has been shown to be a reliable and versatile tool and the case analysis presented in this work illustrates its significant role. In this paper, a 3D-PICS capacitor used as an element of a band pass filter of a cardiac detection chain was studied. As the electrical and physical diode current signature of this device did not satisfy the targeted needs, a complete failure analysis flow was performed, including OBIRCH and Scanning Capacitance Microscopy characterizations. SCM accumulated measurements allowed extracting and validating a trend according to electrical performance variations from the center to the edge of the wafer. As a result, the root cause of the level of this diode reverse current was identified and corrective actions could be introduced in the process to meet the application requirements.
Proceedings Papers
ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 403-405, November 13–17, 2011,
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The oxide-nitride-oxide (ONO) is one of the critical layers in the deep trench (DT) capacitor of the modern DRAM structure. This paper highlights a ONO inspection methodology, which used the silicon wet etching to enhance the ONO leakage point. First, a hole was milled nearby the leakage ONO, which was localized by using focused ion beam (FIB). Then, silicon was removed by an etching solution from the opening. When the poly of DT is etched through the ONO weak point, the leakage site will be enhanced. With the silicon wet etching enhancement, the ONO leakage point is easy to be observed by X-S FIB inspection. The real ONO leakage point is useful information for the root cause finding and the process improvement.
Proceedings Papers
ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 298-300, November 4–8, 2007,
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Series capacitors, under certain conditions, within high speed differential pair signals were found to have negative effects on mother board functions inside a personal computer (PC). It was noted in one case study that three conditions affected capacitors with this type of application: capacitor aging, DC offset voltage, and cold temperatures. These conditions led to the decrease in capacitance which then disabled the network connection inside the PC. It was concluded that a strategically chosen capacitor type alleviates these conditions. The capacitor type primarily depends on the dielectric material.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 142-146, November 12–16, 2006,
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This paper presents the result of a study of a particular failure mechanism of BaTiO3 MLCC (multiple layer ceramic capacitor). A unique technique of cross-section alternating with emission microscope analysis is developed to precisely locate the failure site for capacitors exhibiting low leakage current in μA range. Thermal Imaging Microscope, Photon Emission Microscope, SEM, STEM/EDS and TEM electron diffraction pattern are employed for the characterization of these low leakage failures. Evidence of high concentration impurities are detected in the dielectric layer of BaTiO3 grain boundaries as well as inside certain grains. TEM diffraction imaging at the failure site shows distinguishingly different diffraction patterns within the matrix of BaTiO3 crystal structure. The evidences point to a combination of impurities at grain boundaries and BaTiO3 crystal change induced by impurity as the failure mechanism.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 185-187, November 12–16, 2006,
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This paper presents a novel method to inspect deep trench (DT) planar profiles at any particular depths using the mechanical polishing method instead of the Focused Ion Beam (FIB) milling method. The sample is polished at a small beveled angle and then inspected in the Scanning Electron Microscope (SEM). This method creates a large area for the inspection of DT profiles. It is accurate and fast in providing the result on process evaluation and failure analysis. Since the FIB is not needed, it is also simple and cost effective.
Proceedings Papers
ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 262-265, November 6–10, 2005,
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Poly/metal stacked capacitors present challenges in terms of capacitor access and defect localization. As for defect localization, liquid crystal or thermal localization (also OBIRCH/TIVA) and passive voltage contrast (PVC) are used. PVC was found to be effective in terms of finding the bad stacked capacitor and a bad capacitor within the stack. This paper highlights brief process steps in 3-layer polysilicon/metal stacked capacitors. It discusses FA on stacked capacitors, providing information on fault isolation and capacitor access. It presents a case study on differentiating defective capacitors which failing due to vertical shorting. Internal probing between the capacitors within a stack allowed the differentiation between capacitor leakage and capacitor-capacitor shorting. For capacitor leakage, the defect can be identified by parallel lapping to remove the upper capacitor plate. For capacitor-capacitor short, if there is no visual defect seen, Pt chemical etch can be applied for PVC inspection.
Proceedings Papers
ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 465-470, November 14–18, 2004,
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This paper studies the effects of an electron beam and an ion beam in sample preparation at the borderless bit-line contact (CB) between a transistor and a bit line in a deep trench capacitor DRAM [1] using the Transmission Electron Microscope (TEM) and the Electron Energy Loss Spectroscope (EELS). An abnormal region in the Si substrate was observed using cross-sectional TEM (XTEM) analysis at both the opened and un-opened CB contacts when normal sample preparation procedures were applied. CBED (Convergent Beam Electron Diffraction) in the TEM verifies this region is a structure of amorphous Si. The EELS spectrum shows the relative thickness (t/λ) of the TEM sample at this amorphous region is similar to that of the single crystal Si substrate. Experimental results demonstrated that this region was the result of radiation damage caused by either the ion-beam scan or the ion-beam Pt metal deposition required for sample preparation in the Focused Ion Beam (FIB) system. This radiation damage was not caused by inline wafer processing. However, the radiation damage zone for an un-opened contact is smaller than that for an opened contact. The size of the radiation damage zone increases relative to the time of the ion beam exposure. Using electron-beam scan and electron-beam Pt metal deposition can prevent this radiation damage from occurring.
Proceedings Papers
ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 437-439, November 2–6, 2003,
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Advanced RF IC’s incorporate numerous components along with the CMOS circuitry. One component is a metal-insulator-metal (MIM) capacitor. Test capacitors have been stressed using accelerated voltage and temperature conditions to assess the long-term reliability. This paper describes a methodology for evaluating the MIM capacitors that have failed during reliability testing. IR microthermography was developed to detect leakage locations in areas that are not visible to optical inspection or standard emission microscopes. These areas were deprocessed to correlate the IR emission and physical defect locations. This information is utilized to understand the failures and improve the reliability.
Proceedings Papers
Failure Analysis of Plasma-Induced Submicron CMOS IC Yield Loss by Backside Photoemission Microscopy
ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 109-113, November 11–15, 2001,
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Backside photoemission microscopy [1-2] was used to analyze the major yield loss of a communication product fabricated with submicron CMOS process: functional failures of phase-lock-loop (PLL). The PLL block was covered by five metal layers and three of them were bulk metals. Based upon the backside photoemissions detected on the capacitor structures within the PLL block and the ruptures observed at the emission spots on the polysilicon and gate oxide or of the capacitor after physical deprocessing, the failure was proved due to the capacitor gate-oxide breakdown. This was believed to be caused by the plasma-induced-damage during high-density-plasma (HDP) CVD oxide deposition after the front-end processes, as only the lots from one HDP-CVD deposition equipment have very high percentage PLL functional failure. Subsequent machine commonality check did find non-uniform inter layer dielectric (ILD) thickness from this equipment, which indicated the non-uniform plasma intensity occurred during the ILD film deposition. This was further confirmed by the finding of a worn-out gas-shower-head in this system. The abnormal high density of plasma created extra charging and caused the PLL poly capacitor’s gate oxide breakdown due to the antenna effect. After replacing the gas showerhead, the failure disappeared and yield was back to normal. Through this low yield analysis, we demonstrated an effective application of backside photoemission microscopy to fab yield improvement.
Proceedings Papers
ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 331-341, November 11–15, 2001,
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The continuous scaling of memory technology drives, among other things, an increasing vertical integration. The storage capacitor of a memory cell can be formed as a deep trench into the Silicon to allow high capacitance with a minimum footprint. This paper summarizes preparation techniques especially developed for vertical dielectrics, which are used, for example for the deep trench storage capacitor and the vertical access transistor for this capacitor. The preparation methods employ mechanical polishing, focused ion beam milling and chemical etching to allow for some of the best possible inspection in SEMs and TEMs.
Proceedings Papers
ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 447-450, November 11–15, 2001,
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A failure mode occasionally observed in multilayer ceramic capacitors (MLCC) is degradation of insulation resistance as the capacitor ages under temperature and electrical stress. The dielectric in MLCC can have a heterogeneous appearance when examined by optical microscope or SEM. This makes it difficult to identify features that could explain the root cause of failure or that could be used in devising inspection criteria for lot acceptance. Conventional cross sectioning in an epoxy mount leaves the sample unsuitable for examination in highvacuum equipment such as field emission scanning electron microscopy or Auger Electron Spectroscopy (AES) because epoxy outgasses and badly contaminates the high vacuum system. A novel twostep potting technique for sample preparation and inspection was developed to meet these challenges. This technique enabled us to perform electricallymonitored cross sectioning in combination with thermal inspection (infrared microscopy). Once a shorting site was identified, the sample was easily removed from the epoxy mount, allowing examination of the actual location of the short circuit in the field emission SEM (necessary to avoid sample charging). By precisely identifying the defect site, the chemistry of the defect could then be determined using electron spectroscopy and materials identification techniques [1,2,3].
Proceedings Papers
ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 451-455, November 11–15, 2001,
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In this paper, the investigation process for the failure cause of tantalum capacitors is presented. The capacitors failed during the temperature/humidity testing by reversed polarization. The failed capacitors had higher leakage current. The external visual and Xray examination didn’t show any anomalous phenomena. After cross sectioning and SEM examination, it was found that silver migration is the root cause for the failures.
Proceedings Papers
ISTFA2000, ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis, 225-230, November 12–16, 2000,
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Focused ion beam (FIB) techniques are continuously improved to meet the demands of shrinking device dimensions and new technologies. We developed a simultaneous milling and deposition FIB technique to provide electrical contact to small buried targets in semiconductors. This method is applied to directly connect the deep trench (DT) capacitor of a DRAM single cell in deep submicron technology. By carefully adjusting the deposition parameters (scanned area < (0.3 µm)2, beam current < 20 pA) we are able to influence diameter, depth and Pt fill properties of the hole to meet the very restricted requirements for successful DT connection (hole diameter < 200 nm at DT level). Electrical measurements are performed on DRAM single cells after connecting buried plate (n-band), p-well, wordline, bitline and DT. The probe pads were Pt, deposited with ion beam assistance, on top of highly insulating SiOx, deposited with electron beam assistance by using a dualbeam FIB. The read and write conditions of an active memory cell are studied. The presented method increases the capabilities to localize and characterize trench related failure mechanisms.
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