Skip Nav Destination
Close Modal
Update search
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
NARROW
Format
Topics
Subjects
Article Type
Volume Subject Area
Date
Availability
1-3 of 3
Copper plating
Close
Follow your search
Access your saved searches in your account
Would you like to receive an alert when new items match your search?
Sort by
Proceedings Papers
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 227-230, November 9–13, 2014,
Abstract
View Paper
PDF
In this work, we present TEM failure analysis of two typical failure cases related to metal voiding in Cu BEOL processes. To understand the root cause behind the Cu void formation, we performed detailed TEM failure analysis for the phase and microstructure characterization by various TEM techniques such as EDX, EELS mapping and electron diffraction analysis. In the failure case study I, the Cu void formation was found to be due to the oxidation of the Cu seed layer which led to the incomplete Cu plating and thus voiding at the via bottom. While in failure case study II, the voiding at Cu metal surface was related to Cu CMP process drift and surface oxidation of Cu metal at alkaline condition during the final CMP process.
Proceedings Papers
ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 24-28, November 14–18, 2004,
Abstract
View Paper
PDF
This paper will demonstrate a new copper (Cu) electroplating technique [1] for accurately isolating high resistance fault locations with resistance below K-order ohms. This phenomenon is achieved by having different electric field intensity leading to different copper deposition rate on the sample surface. From experiments, the interface between the thicker electroplated and thinner electroplated copper layer on the sample surface accurately indicates the high resistance fault location. Also, Optical Microscope (OM) and Focused Ion Beam (FIB) are used to inspect the localized fault site of the electroplated sample. Furthermore, this technique, Electro-Plating Localization Method (EPLM), can process several samples or the entire wafer at the same time. In addition, this technique can be applied in the fully open cases of test vehicles with logical circuit as voltage contrast localization method.
Proceedings Papers
ISTFA2001, ISTFA 2001: Conference Proceedings from the 27th International Symposium for Testing and Failure Analysis, 217-224, November 11–15, 2001,
Abstract
View Paper
PDF
As logic technologies ramp to 0.13 µm and beyond, integrating lower resistance dual damascene copper plated BEOL interconnects with low k (k = 2.65) processing with Dow Chemical’s SiLKTM dielectric and with silicon-on- insulator (SOI) technology offers even higher performance (> 1GHz) RISC microprocessor operation [1,2]. Such low k dielectric films dramatically reduce the line-to-line capacitance over conventional silicon dioxide dielectric films as well as FSG (fluorinated silicon glass) dielectric films. Electrical characterization of submicron copper interconnects with SiLKTM offer challenges not present with SiO2 or with FSG dielectric films. Similarly, deprocessing such low-k dielectric films require approaches very different than for silicon dioxide dielectric films or even FSG films. Conventional tungsten contact probe techniques and even FIB deposited pads for submicron probing present concerns as applied to low-k dielectric films. Alternative techniques in electrical probing employing atomic force microscopy (AFM) surface imaging may provide a solution. This technique combines the capability to precisely position multiple probe tips within a small footprint and to perform electrical measurements on features as small as 0.10 µm. The low total input capacitance loading with this technique is applicable to AC waveform characterization for higher speed RISC microprocessor designs.