In this work, we present TEM failure analysis of two typical failure cases related to metal voiding in Cu BEOL processes. To understand the root cause behind the Cu void formation, we performed detailed TEM failure analysis for the phase and microstructure characterization by various TEM techniques such as EDX, EELS mapping and electron diffraction analysis. In the failure case study I, the Cu void formation was found to be due to the oxidation of the Cu seed layer which led to the incomplete Cu plating and thus voiding at the via bottom. While in failure case study II, the voiding at Cu metal surface was related to Cu CMP process drift and surface oxidation of Cu metal at alkaline condition during the final CMP process.

Accelerated corrosion leading to system failure has been observed on printed circuit boards present in industrial environments that contain abnormal levels of reduced sulfur gasses, such as hydrogen sulfide (H2S) and elemental sulfur. The problem is compounded by the fact that elemental sulfur is regulated by OSHA as a nuisance dust, and is allowed in a human working environment at the parts per thousand levels. Anecdotal data shows clearly that elemental sulfur gas present at the parts per million level can cause computer systems to fail within 2 months of use. Newer technologies such as immersion silver plating are especially susceptible to this type of corrosion. With the rapid growth of organically coated copper (OCC) and immersion silver platings, the number of failures due to reduced sulfur gasses in the environment has risen substantially.

This paper will demonstrate a new copper (Cu) electroplating technique [1] for accurately isolating high resistance fault locations with resistance below K-order ohms. This phenomenon is achieved by having different electric field intensity leading to different copper deposition rate on the sample surface. From experiments, the interface between the thicker electroplated and thinner electroplated copper layer on the sample surface accurately indicates the high resistance fault location. Also, Optical Microscope (OM) and Focused Ion Beam (FIB) are used to inspect the localized fault site of the electroplated sample. Furthermore, this technique, Electro-Plating Localization Method (EPLM), can process several samples or the entire wafer at the same time. In addition, this technique can be applied in the fully open cases of test vehicles with logical circuit as voltage contrast localization method.

This paper correlates the reseat failure rates of a PCI option card to the use of thin gold plating across the contact fingers. This failure mechanism results in increased contact resistance and is often misdiagnosed due to its intermittent failure mode. As many new manufactures appear in Asia, the push for global competitiveness to achieve high volume and reduced costs can result in insufficient plating finishes being applied to the contact fingers. Compounding this problem is the fact the many companies use multiple raw board suppliers to meet these volume requirements. Many times the end user of the option card is unaware of the wide variation in contact plating thickness that may be present from one raw board source to another. Intermittent failures are one of the most common defects experienced in high volume assembly. Unless properly diagnosed, these failures can be attributed to finger debris, rework flux, solder paste contamination and even connector related issues. The typical fix, whether approved by the process or not, is for the manufacturing assembler to reseat all of the option cards and memory into the Motherboard connector sockets. Unless the proper troubleshooting approach is followed, isolating the true root cause of the actual failure can be missed. The difficulty in identifying the reseat problem is compounded by the fact that the failures are often intermittent in nature. While reseating may temporarily achieve sufficient mating between the board’s contact fingers and the connector contacts, it provides no long term fix. These unnecessary reseats also reduce the long-term durability of already thin plating affecting customer satisfaction and warranty costs. In the paper, we will expand on the theory behind the XRF plating thickness testing, including: • System theory • Test calibration • Part orientation • Test measurement criteria Additional analysis of metallurgical cross-sectioning was performed to correlate the XRF test readings to the actual plated layers. The measurements were completed by use of a SEM (Scanning Electron Microscopy).

As logic technologies ramp to 0.13 µm and beyond, integrating lower resistance dual damascene copper plated BEOL interconnects with low k (k = 2.65) processing with Dow Chemical’s SiLKTM dielectric and with silicon-on- insulator (SOI) technology offers even higher performance (> 1GHz) RISC microprocessor operation [1,2]. Such low k dielectric films dramatically reduce the line-to-line capacitance over conventional silicon dioxide dielectric films as well as FSG (fluorinated silicon glass) dielectric films. Electrical characterization of submicron copper interconnects with SiLKTM offer challenges not present with SiO2 or with FSG dielectric films. Similarly, deprocessing such low-k dielectric films require approaches very different than for silicon dioxide dielectric films or even FSG films. Conventional tungsten contact probe techniques and even FIB deposited pads for submicron probing present concerns as applied to low-k dielectric films. Alternative techniques in electrical probing employing atomic force microscopy (AFM) surface imaging may provide a solution. This technique combines the capability to precisely position multiple probe tips within a small footprint and to perform electrical measurements on features as small as 0.10 µm. The low total input capacitance loading with this technique is applicable to AC waveform characterization for higher speed RISC microprocessor designs.

The use of an antireflection coating for backside semiconductor failure analysis is discussed. The process of selecting an appropriate coating is described. Several known coatings are also described in regards to imaging quality, material properties, and the benefits to device analysis applications.

High temperature gold/tin eutectic (80 Au/ 20 Sn) solder is used in manufacturing for multiple reasons. These motives may include the ability to post solder a part/device without reflow, high temperature field applications, and allow soldering to thick Au layers without the possibility of precipitating AuSn4 brittle intermetallics. In the following military case, Au/Sn eutectic was employed because of high temperature service and the guarantee of no occurrence of gold embrittlement when soldering to the thick Au outer plating. The Au was plated over an electroplated nickel (Ni) layer on a Kovar (iron/nickel/cobalt) housing. The soldering resulted in an extremely poor bond strength of a duroid circuit to the Kovar housing. The results showed contamination in the supplier’s electroplated Ni bath caused the plating to have poor bond strength. The failure occurred within the Ni plating layer.

We investigated the cause of the whisker/discoloration which were found in the transistor lead of stocks (package type TO-18, low power use). In process of the investigation, we estimate two corrosion models that the first model is the remnant of sulfuric acid in cracks of the nickel-phosphorus plating layer in the transistor lead, the second model is the out-gassing or the dissolved ions from the stock container and conductive mat. As the results of the investigation which includes analyses of the whisker/discoloration cross section made by FIB (Focused Ion Beam), a reproductive experiment and so on, the whisker/discoloration were the corrosion reacted between the solder (Pb-Sn) on the transistor lead and SO 4 2- ions of the stock container. We estimate that the new corrosion will not occur and grow in mounted devices because of rejecting the source of corrosion (stock containers). Further, in the worst case of the corrosion occurrence, protective coatings were applied to the mounted transistor lead, as the measure against falling away from the transistor lead.

Mechanical strength, integrity, and reliability of solder connections used in the microelectronics industry are important factors in overall quality and reliability of the finished product. In most cases tin (Sn) rich solders are attached to a base metal plated with nickel (Ni) and then with gold (Au). Formation of AuSn4 intermetallics in the solder may result in loss of more than 80% of the initial impact toughness, resulting in loss of reliability of the connection. Gold (Au) embrittlement is a major concern in tin/lead (Sn/Pb) soldering or any other joining process with Au and Sn as major constituents. Noncompliance to Au plating-thickness specifications by vendors or insufficient Sn wicking of Au surfaces can result in embrittled joints and unreliable parts.

At the surface of the tin-plated brass substrate placed at 50°C, the tin whiskers grew evidently within a short time, due to the formation of zinc oxide on the surface and alloying between plated tin and brass substrate as supposed. While at the surface of the brass substrate plated with tin on nickel, there was no trace of the tin whisker at all. Nickel greatly represses the diffusion of base metal materials into the tin layer. Nickel and tin plated monolithic chip capacitors placed at the same condition for 18 years were also observed and the tin whisker growth phenomenon has never taken place either. As a result, the tin plated film on the nickel over silver thick film does not provide the tin whisker growth. Nickel underplating plays an important role in tin plated capacitors for not only the solder leaching but also the tin whisker growth problems.