This paper introduces the use of machine learning models in the characterization of bitmap fail patterns occurring on SRAM to identify FEOL/MEOL layers defectivity distribution. The results of bitmap patterns with test conditions are used for fault analysis post-processing and manufacturing yield improvement methodologies. Several machine learning models were built for prediction of the FEOL/MEOL layer defects based on hundreds of bitmap physical failure analysis results. A model utilizing a multilayer perceptron (MLP) architecture with backpropagation of error were optimized and it can be easily applied to volume products with millions of bitmap test results with >80% accuracy. It is the first time we are able to investigate the FEOL/MEOL defects density quantitatively through an automatic diagnosis tool.

Failure to apply the proper systematic analysis procedure can result in loss of valuable evidence required to understand the root cause of package failures. For example, in the case of marginal current leakage fail, decapsulation from package front-side may result in loss of the electrical failure signal so that root cause of the leakage failure cannot be understood. In such case, a systematic backside fault isolation method can improve the success rate of isolating the defect. These electrical failures are often due to zero solder bond line thickness (BLT), or filler particle compression on the die, which are key assembly defects encountered in clip style surface mount packages (SMX). In this paper, the first case study is to determine the failure mechanism of an electrical short. A silicon micro-crack propagating through the junction at the dimple clip center, which is due to the ultra-thin solder BLT close to zero micron is found to be the root cause of failure. The second case presents the failure mechanism for a low leakage fail. The pointed tip of a silica filler particle compressed on the die surface leads to excessive leakage.

This presentation provides an overview of the terminology and concepts associated with semiconductor yield analysis, modeling, and improvement techniques. It compares and contrasts yield models and describes the steps and equipment involved in setting up yield engineering programs targeting specific failures and defects. It also includes case histories showing how different yield analysis models have been used to identify the root cause of random and systematic failures.

This paper describes a project to develop and deploy a systematic screening methodology involving computed tomography (CT) to inspect a set of electromagnetic interference (EMI) filter components for a spacecraft application. The goal was to deploy the nondestructive CT test to replace the destructive test method typically deployed for such components. The paper describes the development of test criteria, fixturing, inspection process, and data analysis, including quantitative image analysis of voids and cracks. The initial results indicated that the parts would not pass the requirements established in the test design. A waiver was written to the project clarifying that if the parts were to be used in the assembly, they should be considered as simple conductors with EMI filtering capability viewed as an added benefit rather than a guaranteed design requirement.

Static random access memory (SRAM) can occupy up to 90% of the die surface in a microprocessor and is often laid out with even more aggressive design rules than logic circuitry, which makes it more prone to manufacturing defects and more sensitive to process variations. As a result, SRAM is often chosen to be the process qualification vehicle during technology development and the yield learning vehicle during product manufacturing. Consequently, fast and accurate analysis of SRAM failure is critical to success on many levels. In this paper, we present a defect identification method that combines design for test (DFT) features, direct bitcell access (DBA), and nondestructive fault isolation techniques. With examples and case studies, it is shown how the approach makes use of electrical failure analysis data to greatly reduce the cycle time of root cause identification in the early stages of new technology development.

In this paper, we discuss the use of spontaneous photon emission microscopy (PEM) for observing filaments formed in HfO 2 resistive random access memory (ReRAM) cells. The setup employs a CCD and an InGaAs camera, revealing photon emissions in both forward ( set ) and reverse ( reset ) bias conditions. Photon emission intensity is modeled using an electric-field equation and inter-filament distance and density are determined assuming a uniform spatial distribution. The paper also discusses the use of high frame rate and prolonged photon emission measurements to assess lifetime and reliability and explains how single filament fluctuations and multiple filaments in a single cell were observed for the first time.

This paper presents a novel approach for detecting channel hole bending (ChB) defects in vertical NAND flash memory. Such defects are the result of etching process inconsistencies and contribute to data loss and device failure by inducing leakage current between adjacent channel holes. In order to satisfy long-term reliability requirements and volume demand, chipmakers must be able to detect these defects prior to shipping during electrical die sorting and screening procedures. The proposed method works by monitoring leakage current differences between diagonally and horizontally adjacent memory cells and is shown to be an effective screening technique.

We have adopted various defect detection systems in the front stage of manufacturing in order to effectively manage the quality of flash memory products. In this paper, we propose an intelligent pattern recognition methodology which enables us to discriminate abnormal wafer automatically in the course of NAND flash memory manufacturing. Our proposed technique consists of the two steps: pre-processing and hybrid clustering. The pre-processing step based on process primitives efficiently eliminates noisy data. Then, the hybrid clustering step dramatically reduces the total amount of computing, which makes our technique practical for the mass production of NAND flash memory.

This presentation provides an overview of the terminology and concepts associated with semiconductor yield analysis, modeling, and improvement techniques. It compares and contrasts yield models and describes the steps and equipment involved in setting up yield engineering programs targeting specific failures and defects. It also includes case histories showing how different yield analysis models have been used to identify the root cause of random and systematic failures.

The trends towards 3D integration in microsystems technology and electronic packaging require that failure-analysis methods and target-preparation procedures are adapted to these emerging packaging technologies. The feasibility of laser-target preparation in microsystems is addressed in this paper, especially 3D integrated electronic devices. Various laser technologies were evaluated and the laser of choice was demonstrated to be appropriate for use with stacked packages. In addition, the laser preparation related Heat-Affected Zones (HAZs) were studied. The laser-energy absorption was determined by in situ heating-rate measurement, which enables precise prediction of HAZ extension by the use of Finite Element (FE) simulation. The advantage of this technique for removal rates compared to conventional techniques is discussed, as well as the combination of the excellent ablation rates of pulsed-laser ablation with the high accuracy of Focused Ion Beam (FIB) milling.

It has been found that a process-design interaction involving very large capacitor arrays is capable of causing voiding in well-formed copper trenches. This voiding is believed to be caused by the electrochemical dissolution of copper driven by the photovoltaic effect realized at p-n junctions. A series of experiments was performed to reproduce this voiding in a laboratory environment using water and exposure to light or dark. The experiments were performed on two different size capacitor arrays. In addition, similar experiments were performed on a large capacitor array that uses the opposite dopant isolation scheme. Conversely, copper dendrite growth was observed at the features of interest instead of dissolution, even under flowing de-ionized water (DI) conditions. The results are discussed in the context of known copper-water electrochemical equilibria and design implications are discussed.

The bump nodule growing in electroplating process could be large enough to induce bump to bump short even if the nodule would be weaken by re-flow process. In this work, the microstructure of PbSn eutectic bump and Au bump nodules was analyzed with FIB, SEM and EDS. In PbSn eutectic bump nodule, void defects can be observed with FIB imaging. In Au bump nodule, radiation-like grain structure around the center of Silicon-contained particle can be observed. Based on those analysis results, voids and particles are the source of bump nodule growth. The reason for bump nodule formation is that particles, voids and cathode morphology defects change the roughness of cathode surface, which induces a higher current density area and accelerate local electrocrystallization. Generally, particles, voids and cathode morphology defects are caused by poor photolithography process, tank corrosion and anode contamination such as passivation membrane. Therefore, three conclusions are proposed in this work: 1) where and when the nodules grow can be identified according to their microstructures; 2) cleaning tank and anode periodically can effectively prevent the bump nodules; 3) Qualified photo resist (PR) coating and PR opening process are essential to prevent bump nodule defects.

X-ray fluorescence imaging is a novel non-destructive method to obtain sub-100nm spatial resolution elemental maps with short data acquisition times. The method has a wide range of applicability in the field of semiconductor manufacturing and semiconductor failure analysis. Imaging of copper interconnects on ICs for the location of voids and shorts is one particular application that is relevant for current and future needs of nondestructive inspection and failure analysis of backend processes.

In this paper, scanning thermal conductivity microscopy is used to characterize interconnect defects due to electromigration. Similar features are observed both in the temperature and thermal conductivity micrographs. The key advantage of the thermal conductivity mode is that specimen bias is not required. This is an important advantage for the characterization of defects in large scale integrated circuits. The thermal conductivity micrographs of extrusion, exposed and subsurface voids are presented and compared with the corresponding topography and temperature micrographs.

The critical impact of corner voids on the anticipated reliability of CSP subjected to mechanical stresses is demonstrated in this paper. Experimental and numerical simulation results indicate that the presence of a corner underfill void subjects the solder joint to stress values approaching that of a non-underfilled CSP. In the absence of underfill voids, the reliability in drop testing improved when the CSP was underfilled, and the improvement was inversely proportional to the modulus of the underfill in the range studied. Results indicate that underfill quality could potentially play a critical role in determining reliability in the field for products subjected to mechanical loading.

This paper presents the problems, the solutions, and the development state of the novel 0.18 μm Cu Metal Process through failure analysis of the Alpha CPU under development at Samsung Electronics. The presented problems include : “Via Bottom Lifting” induced by the Cu Via void, “Via Bottom dissociation” due to the IMD stress, “Via side dissociation” due to the poor formation of the Barrier Metal, “Via short/not-open failure” due to the IMD lifting, and Cu metal Corrosion/Loss. The analysis was carried out on the Via Contact Test Chain Patterns, using the “Electron (ION) Charge Up” method. After carefully analyzing each of the failure types, process improvement efforts followed. As a result, the pass rate of the via contact Rc was brought up from a mere 20% to 95%, and the device speed higher than 1.1 GHz was achieved, which surpasses the target speed of 1 GHz.