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Aqueous corrosion
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Proceedings Papers
The Sulfide Contamination Management in Circuit Probing FAB Clean Room Environment
Available to Purchase
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 209-213, November 12–16, 2023,
Abstract
View Papertitled, The Sulfide Contamination Management in Circuit Probing FAB Clean Room Environment
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for content titled, The Sulfide Contamination Management in Circuit Probing FAB Clean Room Environment
Sulfur corrodes silver metal in a continuous reaction. This corrosion is also found in semiconductor industry processes for the application of silver into Backside Grinding & Backside Metal (BGBM). In this paper two experiments were conducted for the sulfide corrosion behavior in a Circuit Probing (CP) clean room environment. They were Mixed Flowing Gas (MFG) and clean room environment exposure test. The MFG test of this research was conducted in a testing chamber with temperature, relative humidity, and concentration of H2S were carefully controlled and monitored. The MFG test conditions included the test temperature of 25°C, relative humidity of 75 %, and H 2 S gas concentration of 10 ppb. And the MFG tests lasted for over 72 hours. The X-ray photoelectron spectroscopy (XPS) was used to analyze the elements composition and Ag 2 S film thickness of the MFG test samples. The second test of this research was the direct exposure experiment. The silicon samples deposited with appropriate silver layer thickness were exposed in CP fab clean room environment with H 2 S concentration well monitored. The XPS analysis results of the corresponding exposure test samples indicated that the Ag 2 S contamination would continue to develop and wouldn't saturate. This would be indicative for the management of Ag 2 S contamination control. The results of MFG and Exposure test were help for Ardentec to setup Ag 2 S corrosion methodology. All the managements were applied into daily operation of the BGBM semiconductor products.
Proceedings Papers
Evaluation of On-Chip ESD Supply Clamp Robustness by In-Situ Floating Power Bus Monitoring
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ISTFA2000, ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis, 195-201, November 12–16, 2000,
Abstract
View Papertitled, Evaluation of On-Chip ESD Supply Clamp Robustness by In-Situ Floating Power Bus Monitoring
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for content titled, Evaluation of On-Chip ESD Supply Clamp Robustness by In-Situ Floating Power Bus Monitoring
Continuous improvements over time to a CMOS Flash Memory technology resulted in significant improvement in Human Body Model (HBM) ESD immunity for “I/O’s” to Vcc power supply and Vss ground pins. Remaining low level failure modes in the die core included elevated standby current that in some cases could not be localized even with extensive chip de-processing. In addition an apparent functional failure upon post stress ATE test was isolated for certain part revisions. Routine separation of Vss/Vcc supply pin combinations from “all other pins” during HBM ESD test allowed identification of the several failures occurring in the die core. Failure analysis and corrective action is described. Additional diagnostic testing using separate polarity HBM pulses aided in tracing the conduction path causing the apparent functional failure and prompted investigation of HBM tester dynamic properties. It was determined that the magnitude of the “second” HBM pulse in certain testers was sufficient to cause a false powerup condition which results in apparent functional failure upon subsequent ATE test. In-situ monitoring of the Floating Power Bus response (in this case Vss) during application of HBM stress to the Input-pad to Vcc-pin combination revealed a transient caused by the “second” pulse that allowed such apparent failures to be invalidated. Further more, monitoring the in-situ floating Vss bus response to the HBM allowed conclusions to be drawn as to the utility of different power bus and Vss/Vcc supply clamp layouts, thereby allowing improvements to die layout to be implemented.
Proceedings Papers
Tin Corrosion Induced by Corrosive De-Ionized (DI) Water
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ISTFA1999, ISTFA 1999: Conference Proceedings from the 25th International Symposium for Testing and Failure Analysis, 141-143, November 14–18, 1999,
Abstract
View Papertitled, Tin Corrosion Induced by Corrosive De-Ionized (DI) Water
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for content titled, Tin Corrosion Induced by Corrosive De-Ionized (DI) Water
Very highly purified water such as De-ionized (DI) water tends to become very corrosive once exposed to the atmosphere. This “Hungry Water” as known in the water purification world is known to be a major source of corrosion [1]. The DI water was responsible for corrosion of tin during autoclave (pressure cooker) testing of Integrated Circuit (IC) devices assembled in plastic Quad Flat Package (QFP) with fine pitch leads. The copper leads of these packages are plated with solder. The copper leads of the packages are plated with solder composed of Lead and Tin. Due to the effect of corrosive water, Tin from solder corroded during the autoclave testing and formed thin whiskers of solder. These whiskers created a leakage path between the leads causing the devices to fail for pin to pin leakage.