Abstract In this paper, we demonstrate with a case study on a nanocapacitor, the capability of transmission electron microscopy in electron holography mode to be a unique in-situ technique for mapping electric fields and charge distributions on a single device. Such precision is necessary to keep pace with shrinking device dimensions and the ever increasing complexity of device architectures.

Abstract In this paper, we describe the technique of on-axis transmission Kikuchi diffraction (TKD) in a scanning electron microscope and demonstrate its use in characterizing nanoscale crystal structures and defects in semiconductor materials and devices. We explain how we modified hardware and software to achieve an effective spatial resolution of 2 nm during orientation mapping without decreasing acquisition speed, indexing quality, and other performance parameters. The paper includes illustrations comparing sample-detector geometries for conventional EBSD, TKD, and on-axis TKD. It also presents examples of the types of images that can be obtained using on-axis TKD, including raw crystal orientation maps, diffraction patterns, pattern quality maps, time-resolved orientation maps showing microstructure evolution, and a sparse sample map showing the distribution of quantum dots on an electron transparent support film.

Abstract Although the physical limits of CMOS scaling should have been reached years ago, the process is still ongoing due to continuous improvements in material quality and analytical techniques. This paper describes one such technique, electron channeling contrast imaging (ECCI), explaining how it is used to analyze nanoscale features and defects. ECCI allows for fast, nondestructive characterization and has the potential for extremely low detection limits. The detection of low-level defects requires measurements over large areas (usually with the help of automation) to obtain statistically relevant data. For example, automated ECCI mapping routines have been shown to quantify crystal defect densities as low as 1 x 10 5 cm -2 in epitaxially grown Si 0.75 Ge 0.25 . The paper presents various methods to reduce measurement time without compromising sensitivity. It also explains how the mapping routine can be optimized to detect extended crystalline defects in III/V layers, selectively grown on shallow trench isolation patterned Si wafers.

Abstract This paper explains how nanoprobe analysis was used to determine the cause of data retention failures in nonvolatile memory (NVM) bitcells. The challenge with such memory cells is that they consist of two transistors with a single control gate in series with a programmable floating gate connected by a shared source/drain active area. With such a layout, there is no way to isolate the control gate from the floating gate, meaning that characterization must be performed simultaneously on both transistors. Having to characterize two transistors connected in series increases the number of potential electrical signature effects not by a factor of two, but rather the power of two, which makes interpreting the results much more difficult. As discussed in the paper, however, the authors used an atomic force probe to verify the bit map of the faulty device and then analyze the failing bit to confirm the programming error and reveal the possible failure mechanism. The failure mechanism was determined based on its electrical signature and a physical analysis of the bitcell location.

Abstract This paper describes the development and implementation of a TEM-based measurement procedure and shows how it is used to determine the verticality or etching angle of channel holes in V-NAND flash with more than 200 layers of memory cells. Despite the high aspect ratio of the region of interest, the method can resolve offsets down to a few nm. Such precision is critical, as the paper explains, because the radius and thus electrical characteristics of each memory cell is determined by the etching angle.

Abstract This paper explains how embedded assist and timing control techniques are being used to improve soft defect screening in nanoscale static random access memory (SRAM). The electrical stress test method is evaluated on advanced FinFET devices. As test results show, resistive and parametric defects that are difficult if not impossible to detect using conventional techniques become visible with the aid of assist and timing control circuits.