Traditionally, reliability defects are addressed by end-of-line electrical measurements and extensive and dedicated testing during packaging. These tests cover almost every known defect condition and ensure product reliability with high confidence, but they occur in the final stage of manufacturing and are quite time intensive. This paper shows that inline reliability metrology based on Raman spectroscopy is an effective approach for early fault detection and can be used to monitor unintended epi growth, strain, lattice defects, stacking faults, dislocations, and post-etch residues. It can also reveal process anomalies and potential material problems. The paper examines the relationship between process parameters and reliability and reviews the enablers of preventive, early-detection inline metrology in the fab.

In this paper, the stacking fault defects in FinFETs are described as the root cause of the PLL failure. Failure analysis approaches such as photon emission microscopy and nano probing were applied to pinpoint the exact stacking fault location in even transistor level and High resolution TEM confirmed the stacking fault defects in the Fin which was isolated by nano probing. RX local density was confirmed as the key factor in stacking fault generation by TCAD simulation. RX new mask with dummy addition was made to mitigate stress and was confirmed to be effective to reduce the compressive strain at the channel in FinFETs by Geometric Phase Analysis (GPA) which provided sufficiently practical local strain measurement data. The GPA techniques demonstrated here are informative for process improvement and failure analysis in FinFET devices. Keywords – Stacking Fault, Geometric Phase Analysis

High performance source/drain (S/D) stress-memorization technology (SMT) has been previously demonstrated to enhance electron mobility in leading edge SRAM NMOS designs. Dislocations initiating from SMT induced stacking faults cause electrical fails in the device. Transmission electron microscopy (TEM) results show that these dislocations can be reduced by controlling certain processing steps following SMT processing.