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Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 203-205, October 31–November 4, 2021,
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Traditionally, reliability defects are addressed by end-of-line electrical measurements and extensive and dedicated testing during packaging. These tests cover almost every known defect condition and ensure product reliability with high confidence, but they occur in the final stage of manufacturing and are quite time intensive. This paper shows that inline reliability metrology based on Raman spectroscopy is an effective approach for early fault detection and can be used to monitor unintended epi growth, strain, lattice defects, stacking faults, dislocations, and post-etch residues. It can also reveal process anomalies and potential material problems. The paper examines the relationship between process parameters and reliability and reviews the enablers of preventive, early-detection inline metrology in the fab.
Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 296-300, October 31–November 4, 2021,
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Vertical-cavity surface-emitting lasers (VCSELs) have many advantages over edge-emitting devices, but they tend to be more sensitive to increasing current density both in lifetime and reliability. To better understand this relationship, the authors investigated the cause of 35 failures involving GaAs-based oxide-confined VCSELs. This paper presents a summary of the procedures, methods, and equipment used, the defects and damages observed, and the root causes behind each failure. The authors followed a standard failure analysis workflow consisting of PEM and OBIRCH fault isolation, plan view TEM to confirm the location and distribution of defects, and cross-sectional TEM (XTEM) to determine the profile of a defect at a specific site. All failures examined could be attributed to one of four basic failure mechanisms: burnout due to ESD, dislocations, oxide diffusion, and oxide delamination.
Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 423-429, October 31–November 4, 2021,
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Global thinning is a technique that enables backside failure analysis and radiation testing. In some devices, it can also lead to increased thresholds for single-event latchup and upset. In this study, we examine the impacts of global thinning on 28 nm node FPGAs. Test devices are thinned to 50, 10, and 3 μm via CNC milling. Lattice damage, in the form of dislocations, extends about 1 μm below the surface, but is removed by polishing with colloidal SiO2. As shown by finite-element modeling, thinning increases compressive global stress in the Si while solder bumps (in flip-chip packages) increase stress locally. The results are confirmed by stress measurements obtained through Raman spectroscopy, although more complex models are needed to account for nonlinear effects in devices thinned to 3 μm and heated to 125°C. Thermal imaging shows that increased local heating occurs with increased thinning, but the maximum temperature difference across the 3-μm die is less than 2°C. Ring oscillators throughout the FPGA fabric slow about 0.5% after thinning and another 0.5% when heated to 125°C, which is attributed to stress changes in the Si.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 476-479, November 6–10, 2016,
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A failure analysis work flow is presented demonstrating dislocation visualization, site isolation, TEM lamella preparation and defect characterization. A novel beam control technique allows visualizing dislocations with significantly improved spatial resolution in SEM using Electron Channeling Contrast Imaging. Site-specific TEM preparation on dislocations is therefore possible. The prepared thin lamella can be inspected in the SEM using STEM to study dislocations. This is a cost effective work flow without using TEM.
Proceedings Papers
ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 313-321, November 3–7, 2013,
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Fault localization on functional macros during advanced technology development requires a complex combination of tester based diagnostics and image based techniques including laser voltage imaging (LVI), laser voltage probing (LVP), critical parameter analysis (CPA) with laser stimulation and photon emission microscopy (PEM). These techniques are exemplified in the following three case studies. The first case involves a voltage sensitive SRAM block fail which was localized to a resistive via through the use of CPA, LVI and LVP. The second case demonstrates how a hard fail (a net-to-net metal short) in a scan chain was localized through use of tester based diagnostics, LVI, LVP and PEM. Finally, the last case shows how a condition sensitive failing latch chain was localized through CPA, LVI, LVP and PEM. Subsequent atomic force probing (AFP) identified source-drain leakage in one of the localized devices, and TEM analysis revealed a dislocation in the failing FET. Each of these cases demonstrates the value in utilizing tester based diagnostics along with laser based imaging and photon emission microscopy to localize failures.
Proceedings Papers
ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 560-562, November 3–7, 2013,
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Plan view TEM imaging is a powerful technique for failure analysis and semiconductor process characterization. Sample preparation for near-surface defects requires additional care, as the surface of the sample needs to be protected to avoid unintentionally induced damage. This paper demonstrates a straightforward method to create plan view samples in a dual beam focused ion beam (FIB) for TEM studies of near-surface defects, such as misfit dislocations in heteroepitaxial growths. Results show that misfit dislocations are easily imaged in bright-field TEM and STEM for silicon-germanium epitaxial growth. Since FIB tools are ubiquitous in semiconductor failure analysis labs today, the plan view method presented provides a quick to implement, fast, consistent, and straightforward method of generating samples for TEM analysis. While this technique has been optimized for near-surface defects, it can be used with any application requiring plan view TEM analysis.
Proceedings Papers
ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 293-296, November 11–15, 2012,
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In this work, delineation of crystal defects in Si by preferential chemical etching (Wright etch) is discussed. Investigation of defects in Si wafers by preferential chemical etching enables the study of various types of crystal defects for large area defect distribution (up to full wafer) and root cause analysis. In the case of dislocation defects, the shapes of etch pits are different for different etching duration. We show the mechanism of the pit shape evolution under preferential etching and suggested the appropriate etching duration for defect type identification with inspection by optical microscopes. The dislocation delineation method has been applied to a case of functional failure of devices caused by abnormal process in Laser Scanning Annealing (LSA). It was shown that the distribution of dislocation defects depends largely on the direction of LSA scan direction. We discuss the relationship between dislocation defect distribution and the density and uniformity of the active-Si patterns as well as possible solutions for elimination of dislocation defects in LSA process.
Proceedings Papers
ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 337-346, November 11–15, 2012,
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Different epitaxial structures have been studied by high-resolution x-ray diffraction and x-ray topography, Transmission Electron Microscopy and Atomic Force Microscopy to establish correlations between epitaxial growth conditions and crystal perfection. It was confirmed that epitaxial growth under initial elastic stress inevitably leads to the creation of extended crystal defects like dislocation loops and edge dislocations in the volume of epitaxial structures, which strongly affect crystal perfection and physical properties of future devices. It was found that the type of created defects, their density and spatial distribution strongly depended on growth conditions: the value and sign of the initial elastic strain, the elastic constants of solid solutions, the temperature of deposition and growth rate, and the thickness of the epitaxial layers. All of the investigated structures were classified by their crystal perfection, using the volume density of extended defects as a parameter. It was found that the accommodation and relaxation of initial elastic stress and creation of crystal defect were up to four stages “chain” processes, necessary to stabilize the crystal structure at a level corresponding to the deterioration power of particular growth conditions.
Proceedings Papers
ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 322-326, November 13–17, 2011,
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In this work, crystalline defects (dislocations) occurred in the silicon substrate during annealing SOD (Spin On Dielectric) which is an easy choice for its superior STI gap-fill ability. The reversal of address data that share same SIO (Signal Input Out) line in a DQ arises from crystalline defects. The failure analysis of physical methods has difficulty finding minute defects within the active because it is scarcely detectable from the top view. Situation can be well understood by electrical analysis using the nano probe. Due to its ability to probing contact nodes around the fail area, a ring type crystalline defect which is hardly detected from the top view was effectively analyzed by 3D TEM with the assistance of nano probe. This work shows that hybrid analysis of electrical method by nano probe and physical method by 3D TEM is useful and effective in failure analysis in semiconductor.
Proceedings Papers
ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 92-97, November 14–18, 2010,
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Failures induced in the silicon substrate by process marginalities or process mistakes need continuous attention in new as well as established technologies. Several case studies showing implant related defects and dislocations in silicon will be discussed. Depending on the electrical characteristics of the failure the localization method has to be chosen. The emphasis of the discussion will be on the importance of the right choice for further physical de-processing to reveal the defect. This paper focuses on the localization method, the de- processing technique and the use of Wright etch for subsequent TEM preparation.
Proceedings Papers
ISTFA2009, ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis, 162-165, November 15–19, 2009,
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In this contribution the use of electroluminescence imaging, bias-dependent lock-in thermography, special dark and illuminated lock-in thermography techniques, and electron microscopy techniques is demonstrated for investigating the physical mechanism of breakdown in multicrystalline silicon solar cells. Two dominant breakdown mechanisms are identified, which are breakdown at recombination-active crystal defects, showing a relatively soft breakdown, and avalanche breakdown at dislocation-induced etch pits, which occurs very steep (hard breakdown) and dominates in our cells at high reverse bias.
Proceedings Papers
ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 315-316, November 2–6, 2008,
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Scanning electron microscope (SEM) and high resolution transmission electron microscope analysis combined with focused ion beam have been used to locate the physical defect. Visualizing the defect by these techniques was found to be difficult. This paper introduces a novel physical failure analysis technique using 3D rotation STEM imaging. It describes the electrical method of analyzing the cause of failure. Trying to determine with 2D imaging if the defect was a crystalline or not was problematical. To resolve the issue, a pillar type of specimen was made by utilizing a 3D rotation holder and observed with the sample from different directions. Results confirmed that the generation of dislocations can occur according to the variation of the stress transferred to the bulk Si. The variation was due to stress intensity and pattern isolation as a function of the film volume of spin on dielectric material and shallow trench isolation size.
Proceedings Papers
ISTFA2007, ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis, 348-350, November 4–8, 2007,
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In reliability test some chips suffered functional failure. Through a series of failure analysis experiments, the root cause was determined to be a silicon dislocation across LDD (Lightly Doped Drain) area causing p-n junction leakage. However, those failed samples all passed both CP (Chip Probe) and FT (Final Test) monitor. Therefore, it is reasonable to suspect that DVS (dynamic voltage stress) may enhance minor dislocations already existing before CP and FT. To prove this hypothesis, an experiment was designed to find the relationship between DVS and the depth of dislocation in silicon substrate. In conclusion, DVS could enhance dislocation across LDD area, which may induce reliability failure. Moreover, reliability concerns on this finding will be discussed in this paper.
Proceedings Papers
ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 59-63, November 6–10, 2005,
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With high implant doses, strained silicon technologies and shrinking feature sizes, dislocation related failures seem to gain more importance in advanced CMOS devices. On the basis of case studies, different types of dislocations as well as the electrical characteristics of the corresponding devices will be presented.
Proceedings Papers
ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 233-234, November 6–10, 2005,
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Traditional plane-view TEM images, which have large fields of view and are usually used to check the existence of dislocations, cannot tell whether a dislocation goes through the p-n junction or not. While XTEM images tell the local depth of a small part of a dislocation only, other methods have to be developed to explore how a dislocation goes in the substrate. In this article, the authors have modified the technique of stereo TEM, which was used to study the 3D shapes of precipitates, to study how a dislocation runs in the Si substrate. Three images recorded after tilting the TEM sample were used for measuring the dislocation depth profile. The distances between a few chosen points on the dislocation and the reference line were measured from above three images. Results suggested that the depth profiles of dislocations in the Si substrate can be accurately determined by stereo TEM.
Proceedings Papers
ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 302-306, November 6–10, 2005,
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By combining transmission electron microscopy (TEM) [1] with scanning capacitance microscopy (SCM) [2], it is possible to enhance our understanding of device failures. At Sandia, these complementary techniques have been utilized for failure analysis in new product development, process validation, and yield enhancement, providing unique information that cannot be obtained with other analytical tools. We have previously used these instruments to identify the root causes of several yield-limiting defects in CMOS device product lines [3]. In this paper, we describe in detail the use of these techniques to identify electrically active silicon dislocations in failed SRAMs and to study the underlying leakage mechanisms associated with these defects.
Proceedings Papers
ISTFA2005, ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis, 344-349, November 6–10, 2005,
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The primary objectives of failure analysis on structurally complex semiconductor devices are often to determine a defect's location and composition. Determining exactly how these defects propagate through a sample in three dimensions, to confirm a failure mode, is often elusive. This paper discusses characterizations of two defect types to illustrate a technique of sequentially imaging whisker type defects from orthogonal orientations using TEM/STEM. The first type is a high resistance short between two metal lines that is best imaged using STEM in order to observe subtle differences in material composition. The second is a crystalline dislocation through an optoelectronic device that is best observed using TEM. Details of resistive short characterization and crystalline defect characterization performed are provided. TEM/STEM has shown to be a practical tool for locating defects prior to cross sectional analysis. This allows defects to be located and characterized in three dimensions.
Proceedings Papers
ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 109-114, November 14–18, 2004,
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In modern integrated circuits (IC) using sub-micron or deep sub-micron process rules, substrate dislocation is a common failure mechanism in SRAM or embedded SRAM products. Depending on the position of substrate dislocation in the SRAM cell, it may result in problems including junction or contact leakage, gate oxide early breakdown, low threshold voltage, and poor data retention. In this paper, we’ll focus on the test methodology and physical failure analysis to dig out the failure mechanism, substrate dislocation under SRAM pass gate and node contact. In addition, we will measure the electrical behavior of such substrate dislocation. Several FA techniques, such as Passive Voltage Contrast (PVC) [1] pad deposition by Focus Ion Beam (FIB), and electrical micro probing [2] will be used during leakage verification and measurement.
Proceedings Papers
ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 120-125, November 14–18, 2004,
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The introduction of p+ implanted areas at the drain side of source-drain-gate salicide-blocked electro-static discharge (ESD) protection diodes resulted in a better ESD robustness, however at the expense of increased leakage currents in up to 40% of the 90nm technology test structures. Leaky devices are found to be randomly distributed across a wafer. The leakage current exhibits only weak temperature dependence and is linearly increasing with the p-implanted area. Photoemission microscopy revealed spots located exclusively in the p+ implanted areas. TEM imaging visualized, that the leakage path is caused by dislocations, reaching from the silicon surface through the p+n junction zone into the substrate. Based on these results and the implant conditions, a theory of dislocation formation was postulated and countermeasures had been defined.
Proceedings Papers
ISTFA2004, ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis, 244-247, November 14–18, 2004,
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The temperature and strain rate effects on the shear properties of selected Pb-free solders were investigated. The experiments were performed using single lap shear specimens. All testing was performed using a standard tensile test metrology. The following results were found: 1) Sn-3.5 wt.% Ag outperformed all the other solders in terms of its mechanical strength at all test conditions due to the formation of Ag3Sn precipitates in the bulk solder and Cu6Sn5 intermetallic formation along the interface. However, ductility was sacrificed as this solder strain hardens. 2) The strength and ductility of the solder joint is strongly dependent on the test temperature and strain rate. Data in this work reflects a decrease in strength and ductility when the test temperature is increased. This phenomenon can be attributed to the increase in energy as temperature is increased to overcome dislocation barriers such as impurities and grain boundaries that impede the motion of dislocation. When strain rate is increased, the amount of plastic deformation experienced by the solder increases and more dislocations are formed. Due to the increase in proximity and number of the dislocations, the net result is that motion of the dislocations are hindered thus requiring more stress to deform the material.
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