Abstract Traditionally, reliability defects are addressed by end-of-line electrical measurements and extensive and dedicated testing during packaging. These tests cover almost every known defect condition and ensure product reliability with high confidence, but they occur in the final stage of manufacturing and are quite time intensive. This paper shows that inline reliability metrology based on Raman spectroscopy is an effective approach for early fault detection and can be used to monitor unintended epi growth, strain, lattice defects, stacking faults, dislocations, and post-etch residues. It can also reveal process anomalies and potential material problems. The paper examines the relationship between process parameters and reliability and reviews the enablers of preventive, early-detection inline metrology in the fab.

Abstract Vertical-cavity surface-emitting lasers (VCSELs) have many advantages over edge-emitting devices, but they tend to be more sensitive to increasing current density both in lifetime and reliability. To better understand this relationship, the authors investigated the cause of 35 failures involving GaAs-based oxide-confined VCSELs. This paper presents a summary of the procedures, methods, and equipment used, the defects and damages observed, and the root causes behind each failure. The authors followed a standard failure analysis workflow consisting of PEM and OBIRCH fault isolation, plan view TEM to confirm the location and distribution of defects, and cross-sectional TEM (XTEM) to determine the profile of a defect at a specific site. All failures examined could be attributed to one of four basic failure mechanisms: burnout due to ESD, dislocations, oxide diffusion, and oxide delamination.

Abstract Global thinning is a technique that enables backside failure analysis and radiation testing. In some devices, it can also lead to increased thresholds for single-event latchup and upset. In this study, we examine the impacts of global thinning on 28 nm node FPGAs. Test devices are thinned to 50, 10, and 3 μm via CNC milling. Lattice damage, in the form of dislocations, extends about 1 μm below the surface, but is removed by polishing with colloidal SiO2. As shown by finite-element modeling, thinning increases compressive global stress in the Si while solder bumps (in flip-chip packages) increase stress locally. The results are confirmed by stress measurements obtained through Raman spectroscopy, although more complex models are needed to account for nonlinear effects in devices thinned to 3 μm and heated to 125°C. Thermal imaging shows that increased local heating occurs with increased thinning, but the maximum temperature difference across the 3-μm die is less than 2°C. Ring oscillators throughout the FPGA fabric slow about 0.5% after thinning and another 0.5% when heated to 125°C, which is attributed to stress changes in the Si.

Abstract In this paper, the stacking fault defects in FinFETs are described as the root cause of the PLL failure. Failure analysis approaches such as photon emission microscopy and nano probing were applied to pinpoint the exact stacking fault location in even transistor level and High resolution TEM confirmed the stacking fault defects in the Fin which was isolated by nano probing. RX local density was confirmed as the key factor in stacking fault generation by TCAD simulation. RX new mask with dummy addition was made to mitigate stress and was confirmed to be effective to reduce the compressive strain at the channel in FinFETs by Geometric Phase Analysis (GPA) which provided sufficiently practical local strain measurement data. The GPA techniques demonstrated here are informative for process improvement and failure analysis in FinFET devices. Keywords – Stacking Fault, Geometric Phase Analysis

Abstract A failure analysis work flow is presented demonstrating dislocation visualization, site isolation, TEM lamella preparation and defect characterization. A novel beam control technique allows visualizing dislocations with significantly improved spatial resolution in SEM using Electron Channeling Contrast Imaging. Site-specific TEM preparation on dislocations is therefore possible. The prepared thin lamella can be inspected in the SEM using STEM to study dislocations. This is a cost effective work flow without using TEM.

Abstract Fault localization on functional macros during advanced technology development requires a complex combination of tester based diagnostics and image based techniques including laser voltage imaging (LVI), laser voltage probing (LVP), critical parameter analysis (CPA) with laser stimulation and photon emission microscopy (PEM). These techniques are exemplified in the following three case studies. The first case involves a voltage sensitive SRAM block fail which was localized to a resistive via through the use of CPA, LVI and LVP. The second case demonstrates how a hard fail (a net-to-net metal short) in a scan chain was localized through use of tester based diagnostics, LVI, LVP and PEM. Finally, the last case shows how a condition sensitive failing latch chain was localized through CPA, LVI, LVP and PEM. Subsequent atomic force probing (AFP) identified source-drain leakage in one of the localized devices, and TEM analysis revealed a dislocation in the failing FET. Each of these cases demonstrates the value in utilizing tester based diagnostics along with laser based imaging and photon emission microscopy to localize failures.

Abstract Plan view TEM imaging is a powerful technique for failure analysis and semiconductor process characterization. Sample preparation for near-surface defects requires additional care, as the surface of the sample needs to be protected to avoid unintentionally induced damage. This paper demonstrates a straightforward method to create plan view samples in a dual beam focused ion beam (FIB) for TEM studies of near-surface defects, such as misfit dislocations in heteroepitaxial growths. Results show that misfit dislocations are easily imaged in bright-field TEM and STEM for silicon-germanium epitaxial growth. Since FIB tools are ubiquitous in semiconductor failure analysis labs today, the plan view method presented provides a quick to implement, fast, consistent, and straightforward method of generating samples for TEM analysis. While this technique has been optimized for near-surface defects, it can be used with any application requiring plan view TEM analysis.

Abstract In this work, delineation of crystal defects in Si by preferential chemical etching (Wright etch) is discussed. Investigation of defects in Si wafers by preferential chemical etching enables the study of various types of crystal defects for large area defect distribution (up to full wafer) and root cause analysis. In the case of dislocation defects, the shapes of etch pits are different for different etching duration. We show the mechanism of the pit shape evolution under preferential etching and suggested the appropriate etching duration for defect type identification with inspection by optical microscopes. The dislocation delineation method has been applied to a case of functional failure of devices caused by abnormal process in Laser Scanning Annealing (LSA). It was shown that the distribution of dislocation defects depends largely on the direction of LSA scan direction. We discuss the relationship between dislocation defect distribution and the density and uniformity of the active-Si patterns as well as possible solutions for elimination of dislocation defects in LSA process.

Abstract Different epitaxial structures have been studied by high-resolution x-ray diffraction and x-ray topography, Transmission Electron Microscopy and Atomic Force Microscopy to establish correlations between epitaxial growth conditions and crystal perfection. It was confirmed that epitaxial growth under initial elastic stress inevitably leads to the creation of extended crystal defects like dislocation loops and edge dislocations in the volume of epitaxial structures, which strongly affect crystal perfection and physical properties of future devices. It was found that the type of created defects, their density and spatial distribution strongly depended on growth conditions: the value and sign of the initial elastic strain, the elastic constants of solid solutions, the temperature of deposition and growth rate, and the thickness of the epitaxial layers. All of the investigated structures were classified by their crystal perfection, using the volume density of extended defects as a parameter. It was found that the accommodation and relaxation of initial elastic stress and creation of crystal defect were up to four stages “chain” processes, necessary to stabilize the crystal structure at a level corresponding to the deterioration power of particular growth conditions.

Abstract High performance source/drain (S/D) stress-memorization technology (SMT) has been previously demonstrated to enhance electron mobility in leading edge SRAM NMOS designs. Dislocations initiating from SMT induced stacking faults cause electrical fails in the device. Transmission electron microscopy (TEM) results show that these dislocations can be reduced by controlling certain processing steps following SMT processing.

Abstract In this work, crystalline defects (dislocations) occurred in the silicon substrate during annealing SOD (Spin On Dielectric) which is an easy choice for its superior STI gap-fill ability. The reversal of address data that share same SIO (Signal Input Out) line in a DQ arises from crystalline defects. The failure analysis of physical methods has difficulty finding minute defects within the active because it is scarcely detectable from the top view. Situation can be well understood by electrical analysis using the nano probe. Due to its ability to probing contact nodes around the fail area, a ring type crystalline defect which is hardly detected from the top view was effectively analyzed by 3D TEM with the assistance of nano probe. This work shows that hybrid analysis of electrical method by nano probe and physical method by 3D TEM is useful and effective in failure analysis in semiconductor.

Abstract In this paper, IR-LBIC (Infrared Light Beam Induced Current) is applied using the laser wavelength of 1064 nm in order to analyze polycrystalline thin-film solar cells. The spatially high-resolved map of the short circuit current (~3 µm) has been obtained by performing the IR-LBIC measurement. The results of the measurement showed higher signal response from the grain boundary compared to that from the grain interior. This difference has been explained by the light trapping effect due to the trench-shaped grain boundary profile, which is possibly accompanied by two stage excitation effects via electronic grain boundary states. It has been additionally investigated, whether LBIC measurement could be used to extract local illuminated cell characteristics. However, since the dark current, which has a decisive influence on the solar cell characteristic, is flowing in the entire cell area, this is not possible. A circuit network simulation demonstrates that LBIC cannot be used for extraction of the local open circuit voltage, and the short circuit current is the only parameter that can be locally defined and therefore clearly observed.

Abstract Failures induced in the silicon substrate by process marginalities or process mistakes need continuous attention in new as well as established technologies. Several case studies showing implant related defects and dislocations in silicon will be discussed. Depending on the electrical characteristics of the failure the localization method has to be chosen. The emphasis of the discussion will be on the importance of the right choice for further physical de-processing to reveal the defect. This paper focuses on the localization method, the de- processing technique and the use of Wright etch for subsequent TEM preparation.

Abstract Crystalline silicon used for fabrication of solar cells, such as multicrystalline silicon (mc-Si), contains a high density of extended crystal defects. Since mc-Si wafers exhibit an inhomogeneous defect distribution, there is a need to combine the spectral capabilities with the ability of spatially resolving the defect areas. This paper reports application of luminescence and electron-beam-induced current (EBIC) techniques for characterization of defects in solar Si. The first part introduces luminescence features of defective Si and discusses application examples. The second part starts with explanation of the EBIC technique, including details about the temperature dependence of the EBIC defect contrast c(T). Then, application examples of the c(T) behavior and the analysis of the "interaction" of grain boundaries with p-n junctions are discussed. The paper demonstrates the potential of luminescence for nondestructive characterization of Si wafers and solar cells in terms of in-line defect detection and process control.

Abstract The temperature dependence of photocurrent of polycrystalline Si (poly-Si) thin-film solar cells on glass with interdigitated mesa structure has been locally investigated using Infrared Light Beam Induced Current (IR-LBIC) in the temperature range of -25 to +70 °C. The temperature dependence of electrical characteristics of poly-Si thin-film solar cells in reverse bias has been also analysed and compared with the monocrystalline thin-film solar cells. The poly-Si solar cell shows a temperature coefficient (TC) for the photocurrent of around +0.8 and +0.6 %/°C in the grain interior and grain boundary, respectively. The activation energy of the reverse current and also the photocurrent due to the IR laser stimulation has been evaluated, which provide information about traps and their energy levels in the absorber layer of the poly-Si thin-film solar cell. The obtained average value of the activation energy associated with the photocurrent of the poly-Si cell suggests the existence of a shallow acceptor level at around 0.045 eV in the grain boundary and 0.062 eV in the grain interior of the absorber layer of the poly-Si thin-film solar cell. The activation energies of the reverse current for poly-Si and monocrystalline cells have been calculated when the device is biased at -1 and -2 V and the results compared with the activation energy of the saturation current obtained from extrapolation of the I-V curve in the SRH (Shockley-Read-Hall) regime. The results show strong voltage dependence. In both cases the activation energy of the reverse current decreases in the reverse bias voltage, approaching the values obtained from the photocurrent.

Abstract In this contribution the use of electroluminescence imaging, bias-dependent lock-in thermography, special dark and illuminated lock-in thermography techniques, and electron microscopy techniques is demonstrated for investigating the physical mechanism of breakdown in multicrystalline silicon solar cells. Two dominant breakdown mechanisms are identified, which are breakdown at recombination-active crystal defects, showing a relatively soft breakdown, and avalanche breakdown at dislocation-induced etch pits, which occurs very steep (hard breakdown) and dominates in our cells at high reverse bias.

Abstract Damage-free gate oxide is one of the important factors to ensure device performance and reliability. Special wafer accepts test structures such as a large size MOS capacitor must be laid on test line to monitor the oxide process issue and process window. However, it brings about many challenges to failure analysis engineer. To overcome the EFA and PFA limitations, fresh samples were taken from the passed wafer and the failed ones to identify the root cause of VBD failure. A novel lapping down method was used to access the capacitor structure. Two VBD failure cases were studied. In this study, poor wet clean process was defined as the cause of the silicon substrate surface damage and crystalline defect. It induced poor oxide deposition, which reduced breakdown voltage. Additionally, 12hrs BOE dip was shown to be an effective method for removing poly and oxide layers from large MOS capacitors.

Abstract A failure incurred in the front-end is typically a bottleneck to production due the need for physical failure analysis (PFA). Often the challenge is to perform timely localization of the front-end defect, or finding the exact physical defect for process improvement. Many process parameters affect the device behaviour and cause the front-end defect. Simply, the failures are of two types: high-resistance and leakage. A leakage mode defect is the most difficult to inspect. Although conductive atomic force microscopy and six probes nano-probing are popular tools for front-end failure inspection, some specific defects still need more effort. The electrical phenomenon and analysis of a crystalline defect will be demonstrated in this paper. The details will be discussed below.

Abstract SRAM memory is an ideal vehicle for defect monitoring and yield improvement during process development because of its highly structured architecture. However, the success rate of defect detection, especially for soft single-column failures, is decreasing when traditional physical failure analysis (PFA) with only the bitmap is available for guidance. This is due to a variety of invisible or undetectable defects that cause leakage in the device. In order to understand the leakage behavior in advanced high voltage (HV) processes, a Conductive Atomic Force Microscope (C-AFM) [1-4] is introduced to perform junction-level fault isolation prior to attempting PFA. According to J. P. Morniroli [5], crystalline defects affect convergent-beam electron diffraction (CBED) and large angle convergent-beam electron diffraction (LACBED) patterns, so CBED and LACBED techniques were also applied to the specimens containing dislocations to allow further characterization of these defects. In this study quantified data extracted using the C-AFM is also used to establish a connection between the failure mechanism discovered and the soft single column failure mode.

Abstract Scanning electron microscope (SEM) and high resolution transmission electron microscope analysis combined with focused ion beam have been used to locate the physical defect. Visualizing the defect by these techniques was found to be difficult. This paper introduces a novel physical failure analysis technique using 3D rotation STEM imaging. It describes the electrical method of analyzing the cause of failure. Trying to determine with 2D imaging if the defect was a crystalline or not was problematical. To resolve the issue, a pillar type of specimen was made by utilizing a 3D rotation holder and observed with the sample from different directions. Results confirmed that the generation of dislocations can occur according to the variation of the stress transferred to the bulk Si. The variation was due to stress intensity and pattern isolation as a function of the film volume of spin on dielectric material and shallow trench isolation size.