During moisture-and-bias reliability stress tests of THBT (temperature and humidity biased test) and HAST (highly accelerated stress test) extensive electrochemical oxidation of a TiN ARC layer is seen to occur. This oxidation proceeds at the nominal temperatures and humidity levels associated with such THBT and HAST tests; excessive heating due to EOS (electrical overstress) or other anomalous electrical conditions was not involved. The oxidation rate increases with applied voltage. Metal line width also affects the spread of oxidation. Oxidation requires the presence of adequate humidity to act as an electrolyte, and therefore is seen to propagate wherever moisture penetration can occur in the passivation dielectrics. The presence of a silicone gel die coating is found to render the die more susceptible to TiN oxidation. Electrical failures – typically open circuits or increased resistance due to corrosion – are found to occur as a consequence of this oxidation and its effect on the surrounding structures. This mechanism is a concern for integrated circuits with TiN in the upper metal layers, operating at voltages >5V in humid conditions. Two approaches at reducing this electrochemical reaction are offered.

In this paper, a comprehensive study to find a memory related yield loss in 90 nm technology will be discussed. The loss was related to spacer bridging, blocking silicide formation and Lightly Doped Drain (LDD), source/drain implant. Soft Defect Localization (SDL) techniques [1], sub-micron Atomic Force Microscope (AFM) probing [2] and Time Resolved Emission (TRE) measurements were necessary to obtain an accurate understanding of the problem and the mechanism. Electrical results were compared to simulations. Modified test structures were implemented to monitor the process stability with respect to bridging failures.

The paper focuses on the pad contamination defect removal technique. The defect is detected at the outgoing inspection step. The failure analysis results showed that the defect is Fluorine type contamination. The failure analysis indicated many source contributors mainly from Fluorine based processes. The focus is in the present work is in the rework method for the removal of this defect. The combination of wet and dry etch processing in the rework routine is utilized for the removal of the defect and preventive action plans for in-line were introduced and implemented to avoid this event in the future. The reliability of the wafer is verified using various tests including full map electrical, electrical sort, gate oxide breakdown (GOI) and wafer reliability level, passivation quick kill to ensure the integrity of the wafer after undergoing the rework routine. The wafer is monitored closely over a period of time to ensure it has no mushroom defect.

Heavy polymer residue has been observed on the sidewall of thick metal during the process release. The thickness of metal line is more than 3 micron. This thick polymer residue on the aluminum metal sidewall is seen from tilt Scanning Electron Microscope (SEM) profile analysis. This polymer residue on the metal sidewall with chlorine ( Cl 2) trapped will result in metal corrosion. The focus on this paper is on the removal of this polymer residue on the thick metal sidewall. The experiments were run with splits of varying the chemical dispensing time and the rinsing time in the process. The success criteria are determined by passing the Defect Source Analysis (DSA) and tilt SEM profile analysis. These wafers are sent for electrical test, wet box test (corrosion test) and electrical sort test to ensure the reliability of the post metal cleaning condition.

Yield enhancement has always been an important topic but even more when processes are moving towards smaller geometries. Today, latest FA flow intends to check wafer quality to monitor production in real-time. The purpose is to adjust any derivation coming from the process as fast as possible. The Atmel-CIMPACA laboratory located in Rousset, France, can do Failure Analysis on wafer, thanks to its wafer prober designed to work on DCG systems equipment and integrated CAD software (Meridian, Emiscope, NEXS software suite). Wafer level yield analysis typically requires long setup and multiple dies analysis. Each of the die can be studied with a set a failure analysis (FA) techniques (photo or thermal) emission microscopy [1], laser stimulation techniques [2] or even dynamic probing using time resolved emission [3],[4] or laser based techniques, for the most common ones [5].

In many cases it is difficult to distinguish mechanical damage from electrostatic surface impacts. In recent years, several investigations have resulted in publications on ESDFOS (Electrostatic Discharge From Outside to Surface). While the diagnostics of the phenomena have been worked out quite well for wafers with aluminum metallization, no formal studies on ESDFOS impact to copper-metallized wafers have been published. This paper investigates physical features of Cu-metallized wafers artificially exposed to ESDFOS impacts of variable severity, producing an understanding of damage features to more easily facilitate recognition of EDSFOS events.

A methodology for detecting silicide pipes on SOI technology in-line soon after their formation is described. Techniques currently exist to detect pipes in-line, but only much later in the process. This methodology, which is based on voltage contrast inspection of test structures, allows experiments to be completed more quickly providing much faster cycles of learning. Two different test structures are described. The first one was designed for other purposes but was adopted for silicide pipe detection at M1. The second was specially designed and allows pipe detection at silicide anneal, W CMP and M1. A procedure for determining the cause of buried shorts detected by the eS32 is also described. Experimental results are presented to demonstrate the benefit of this technique.

Inherently small process margins in patterning are a dominant cause of device yield variability, when process conditions or production lines change. This paper highlights the fact that in spite of a perfect lithographic model, the post OPC variation can be substantial due to manufacturing variability. Pattern integrity is a non-intuitive complex mix of manufacturing process practices combined with manufacturable design practices. Failure analysis is the only effective means for filling the understanding gap for yield management in this case. A case study of yield drop due to layout dependent process marginality and a methodical approach to get to the root of the problem are described in this paper.

The purpose of this paper is to present a systematic analysis methodology for a newly taped-out High Voltage (HV) product that has encountered a 0% yield issue. In order to identify the root cause and improve the yield, a series of electrical analysis experiments designed to reveal the failure phenomenon of the charge-pumping circuit were applied. Combining spice simulation data, I-V curve measurements, CAFM measurements and nano probing, the difference in resistance for a multi-fingered symmetric device was revealed. A deductive method was then used to conduct layout analysis, and an in-line split experiment was developed to explain the failure phenomenon experienced by the multi-fingered HV symmetric device for a charge-pumping circuit.

It has been found that a process-design interaction involving very large capacitor arrays is capable of causing voiding in well-formed copper trenches. This voiding is believed to be caused by the electrochemical dissolution of copper driven by the photovoltaic effect realized at p-n junctions. A series of experiments was performed to reproduce this voiding in a laboratory environment using water and exposure to light or dark. The experiments were performed on two different size capacitor arrays. In addition, similar experiments were performed on a large capacitor array that uses the opposite dopant isolation scheme. Conversely, copper dendrite growth was observed at the features of interest instead of dissolution, even under flowing de-ionized water (DI) conditions. The results are discussed in the context of known copper-water electrochemical equilibria and design implications are discussed.

An effective procedure to determine the Burn-In acceleration factors for 130nm and 90 nm processes are discussed in this paper. The relationship among yield, defect density, and reliability, is well known and well documented for defect mechanisms. In particular, it is important to determine the suitable acceleration factors for temperature and voltage to estimate the exact Burn- In conditions needed to screen these defects. The approach in this paper is found to be useful for recent Cu-processes which are difficult to control from a defectivity standpoint. Performing an evaluation with test vehicles of 130nm and 90nm technology, the following acceleration factors were obtained, Ea>0.9ev and β (Beta)>-5.85. In addition, it was determined that a lower defect density gave a lower Weibull shape parameter. As a result of failure analysis, it is found that the main failures in these technologies were caused by particles, and their Weibull shape parameter “m” was changed depending of the related defect density. These factors can be applied for an immature time period where the process and products have failure mechanisms dominated by defects. Thus, an effective Burn-In is possible with classification from the standpoint of defect density, even from a period of technology immaturity.

During yield ramp, quick turnaround times between production failures and the results of physical failure analysis are essential. In spite of the growing complexity of today's logic designs, a fast defect localization can be done by using diagnostic features implemented within standard test pattern generation tools. The diagnosis result can not only be used for fault localization but also for statistical analysis based on a large number of failing chips. This statistical approach enables the search for systematic yield detractors and leads to a faster product or technology ramp. This paper describes the necessary steps in order to set up statistical scan diagnosis, discusses the main failure analysis strategies and gives experimental results.

This paper shows that in-line voltage contrast inspection can be used to monitor and debug mechanisms causing via and contact opens using ungrounded chain test structures. This opens up a large number of new opportunities to the benefits of in-line VC inspection. A theory explaining the VC appearance of a broken chain is proposed and experimentally verified. The methodology used at IBM’s 300mm fab to apply this phenomenon is described along with some use cases.

As DRAM technology extends into 12-inch diameter wafer processing, plasma-induced wafer charging is a serious problem in DRAM volume manufacture. There are currently no comprehensive reports on the potential impact of plasma damage on high density DRAM reliability. In this paper, the possible effects of floating potential at the source/drain junction of cell transistor during high-field charge injection are reported, and regarded as high-priority issues to further understand charging damage during the metal pad etching. The degradation of block edge dynamic retention time during high temperature stress, not consistent with typical reliability degradation model, is analyzed. Additionally, in order to meet the satisfactory reliability level in volume manufacture of high density DRAM technology, the paper provides the guidelines with respect to plasma damage. Unlike conventional model as gate antenna effect, the cell junction damage by the exposure of dummy BL pad to plasma, was revealed as root cause.

The effect of ash chemistries, N2/H2 and H2, on time-dependent dielectric breakdown (TDDB) lifetime has been investigated for Cu damascene structure with a carbon-doped CVD ultra low-k (ULK, k=2.5) intermetal dielectric. Two failure modes, interfacial Cu-ion-migration and Cu diffusion through the bulk intermetal ULK were attributed to the TDDB degradation for the H2 ash.The interfacial Cu-ion-migration was the only dominated failure mode for the N2/H2 ash. The nitrogen species in the N2/H2 plasma proved to be capable of forming a nitrided protection layer on the surface of the ULK. This nitrided layer suppressed further plasma damage during the ash process and thus lessened the TDDB degradation by preventing Cu diffusion through the bulk ULK.

IC manufacturers, among other things, have to define a global failure analysis (FA) strategy that is best adopted to the challenges associated to the introduction of the 90 and 65 nm CMOS technologies. This article reviews the existing FA techniques and then describes an FA strategy that is aiming at fast, efficient, and economic learning in the latest 120-65 nm CMOS technologies. The strategy is based on a well-balanced mix and usage of in-line defectivity data, voltage contrast analyses, SRAM bitmap analysis results, OBIRCH fault isolation, and various advanced physical characterization techniques. A SRAM bitmap strategy has demonstrated to be very effective in driving most relevant process improvements, and also OBIRCH applied to parametric test structures has helped significantly in identifying major yield detractors.

The formation of silicon defects in 0.18um and smaller technology nodes has become a challenging device level defect to identify and eliminate. In this paper, we present a new method of passive voltage contrast that was initially used to locate silicon defects, experimental results revealing the key contributors to the formation of these defects, and a method of in-line identification by correlating SEM based in-line defect inspections to end of line SRAM fail bit maps. Silicon defects that form along the edge of an active region connect the source and drain with a low resistance leakage path that are successfully detected at later processing layers using voltage contrast techniques with a SEM based In-line inspection tool as well as after processing by using our method of passive voltage contrast. The systematic nature of this defect produces a consistent SRAM memory fail mode of single column fails. When these silicon defects are present, single column fails dominate the usual single and double bit fail modes. The physical location of the failing columns can be mapped back to the defect locations produced from the in-line inspections. This method was utilized to interpret experimental results in an effort to determine process parameters that produce silicon defects. It was found that STI depth plays a key role in the formation of these defects. Experiments were run where the depth was intentionally put at worst case so that the effectiveness of several alternative processes to repair the defects could be evaluated. It was shown that modulating the STI liner oxidation temperature had the largest effect compared to several other process parameters.

Metal interconnect defects have become a more serious yield detractor as backend process complexity has increased from a single layer to about 10 layers. This paper introduces a test methodology to monitor and localize the metal defects based on FPGA products. The test patterns are generated for each metal layer. The results not only indicate the severity of defects for each metal layer, but also accurately isolate open/short defects.

In-line repair of same-level killer defects is suggested as a method of the future for achieving higher yields. A methodology describing selection of killer defects and how to repair them is presented. A proof of concept experiment is presented where killer defects are removed from comb test structures using a FIB. An economic analysis is also included which indicates that this technique is economically viable for more costly chip designs. Therefore additional development work is merited.

During the wafer-sort stage, critical electrical data on the IC chip performance is collected. As technology advances, smaller geometries are continuously implemented to the production line and, as a result, there may be some issues that are difficult to detect and eliminate at the typical wafer-sort or final-test techniques. This paper presents two successful applications of innovative wafer-sort techniques to solve some difficult issues. In the first case, voltage-stress is implemented in the wafer-sort to draw out yield issues which otherwise go undetected. This additional test component helps to screen-out marginal dies and analyze the post-stress spatial pattern. By applying the MERCAD detection system to localize the fault area and the appropriate delayer techniques, metal microbridge is found. In the second case, wafer-sort collects the testing information for the failing scan chains. This information is mapped to the netlist, schematic, and design layout of the chip. Given this information, together with the design layout, the authors are able to narrow down these issues to some metal pattern defects.