Skip Nav Destination
Close Modal
Update search
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
NARROW
Date
Availability
1-5 of 5
Yield Analysis
Close
Follow your search
Access your saved searches in your account
Would you like to receive an alert when new items match your search?
Sort by
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 402-406, November 12–16, 2006,
Abstract
View Paper
PDF
Improving semiconductor yield is a multi-dimensional process that must include design, fabrication, and test aspects. Incorporating design-for-manufacturability (DFM) concepts needs to include prior and ongoing learning and experience on what worked and what did not. As feature sizes shrink beyond 130nm, it is possible to identify another class of failures that is more systematic and related not to manufacturing defects but to DFM marginalities related to layout. In this article, it is shown that DFM can also help reduce design sensitivity to process variations. Examples of these failure modes and the lessons learnt are listed: relaxed design rules for repeated patterns, relaxing design rules to reduce yield loss, and special considerations for analog circuit layout.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 407-411, November 12–16, 2006,
Abstract
View Paper
PDF
The use of memory arrays to drive yield enhancement has driven the development of many technologies. The uniformity of the arrays allows for easy testing and defect location. Unfortunately, the complexities of the logic circuitry are not represented well in the memory arrays. As technologies push to smaller geometries and the layout and timing of the logic circuitry become more problematic the ability to address yield issue is becoming critical. This paper presents the added yield enhancement capabilities of using e600 core Scan Chain and Scan Pattern testing for logic debug, ways to interpret the fail data, and test methodologies to balance test time and acquiring data. Selecting a specific test methodology and using today's advanced tools like Freescale's DFT/FA has been proven to find more yield issues, earlier, enabling quicker issue resolution.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 412-418, November 12–16, 2006,
Abstract
View Paper
PDF
Manufacturing yield is stable when the technology is mature. But, once in a while, excursions may occur due to variances in the large number of tools, materials, and people involved in the complex IC fabrication. Quickly identifying and correcting the root causes of yield excursions is extremely important to achieving consistent, predictable yield, and maintaining profitability. This paper presents a case study of yield learning through a layout-aware advanced scan diagnosis tool to resolve a significant yield excursion for an IC containing 1 Million logic gates, manufactured at 130 nm technology node.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 419-422, November 12–16, 2006,
Abstract
View Paper
PDF
The emergence of multiple core, high speed microprocessors in sub 90nm node technologies present challenges for defect localization, especially in SRAM logic circuits involving Array Built In Self Test (ABIST). Voltage sensitive, temperature sensitive and frequency sensitive soft defects in these ABIST logic circuits can spell the difference between pass and failure, especially for Silicon on Insulator (SOI) designs. High density SRAM arrays with ever shrinking critical dimensions in multiple core, high speed microprocessor designs dictate an increased number of ABIST logic circuits of complex hierarchical design. Scan chain diagnostics to pinpoint the failing scan latch logic circuit following ABIST testing frequently results in ever greater uncertainty; increased number of suspect circuits related to the failure. A case study analysis successfully applied to pinpointing a voltage sensitive logic circuit defect in a 90nm SOI design is described here, followed by root cause TEM analysis.
Proceedings Papers
ISTFA2006, ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis, 423-425, November 12–16, 2006,
Abstract
View Paper
PDF
We investigated the degradation of device reliability due to Negative Bias Temperature Instability (NBTI) of PMOSFET on Strained Silicon on Insulator (S-SOI) substrates for the first time. The degradation has been found to be significantly higher for the S-SOI devices in comparison to SOI counterparts. Subsequent to a Constant Voltage Stress (CVS) during NBTI measurements, a negligible change in the subthreshold swing values was observed. Thus it is believed that generation of fixed charge is responsible for the observed BTI shift in threshold voltage (VTH) and transconductance (GM). Also higher BTI degradation was recorded for short channel devices.