In IDDQ testing of CMOS ASICs (as in conventional voltage based testing) actual defect coverage, rather than modeled fault coverage figures are relevant to achieving product Q&R targets. This paper reports experimental data on the defect coverage of IDDQ vectors taken from several ASICs from different semiconductor suppliers. We present our generic IDDQ methodology that has been run on these ASICs, including automated IDDQ vector generation/grading and the high speed IDDQ monitor OCIMU. Data are presented on absolute IDDO defect coverage, as estimated from correlation with voltage based tests, on the relative defect coverage of pseudo-stuck-at and the toggle fault models, on the defect coverage of reduced IDDQ sets and on the pattern sensitivity Of IDDQ rejects. It is demonstrated that the pictures shown by modeled fault coverage and actual defect coverage can differ significantly and therefore, theoretical fault coverage figures are not the correct data to assure Q&R targets. We have measured very good IDDQ defect coverage on random logic, but we also show real life cases where IDDQ testing alone is inefficient in screening Q&R hazards.

A CAD-based fault diagnosis technique for CMOS-LSI with single fault using abnormal IDDQ has been developed to indicate the presence of physical damage in a circuit. This method of progressively reducingthe faulty portion, works by extracting the inner logic state of each block from logic simulation, and by deriving test vector numbers with abnormal IDDQ. To easily perform fault diagnosis, the hierarchical circuit structure is divided into primitive blocks including simple logic gates. The diagnosis technique employs the comparative operation of each primitive block to determine whether one and the same inner logic state with abnormal IDDQ exists in the inner logic state with normal IDDQ or not. The former block is regarded as normal block and the latter block is regarded as faulty block. The fault of the faulty block can be localized easily by using input logic state simulation. Experimental results on real faulty LSI with 100k gates demonstrated rapid diagnosis times of within ten hours ani reliable extraction of the fault location.

Failure analysis of non-volatile memory arrays can be complicated by the history of bits elsewhere in the array. This generally is in contrast to volatile memories, in which the state of all bits can quickly be reset by over-writing the bits, or by simply removing power from the array. On one of our products, EEPROM bits failed to program if certain patterns of bits were programmed elsewhere in the EEPROM array. During programming, high voltages (>18 volts) are present within the EEPROM array. Such voltage levels caused a narrow field oxide region to break down, thereby pulling down the programming voltage and preventing the successful programming of EEPROM transistors. What complicated the analysis, however, was that the breakdown only occurs if a checkerboard pattern is being programmed in one part of the array, while specific other EEPROM bits had previously been programmed elsewhere in the array. Until the failure mechanism was well understood, electrical screens were difficult to implement, because they typically do not account for complicated interactions between bits. This is especially true for nonvolatile memories, for which test time costs often prohibit the use of complicated test patterns with improved test coverage. This paper reviews the failure analysis, and proceeds to highlight the importance of knowing the contents of nonvolatile arrays prior to performing either failure analysis or automated testing on such an array. The case study therefore applies to both test and failure analysis engineers.

An investigation into latent CMOS device isolation failures during the process development phase of an advanced 0.35 μm CMOS ASIC process is presented. The failure mechanism manifested itself electrically during wafer sort as a non-typical Iddq distribution and subsequently resulted in large leakage failures during reliability stress testing experiments. Emission microscopy analysis on failing units revealed specific leakage sites in the CMOS SRAM core. Layer removal/SEM inspections revealed no physical anomalies in the emission area. Manual toggling of the RAM internal electrical nodes revealed that the leakage occurred through a parasitic field transistor (i.e. between two P+ diffusion islands gated by a polysilicon runner). Probing of test structures with similar layout features revealed that the diffusion isolation between the P+ diffusions was marginal, resulting in subthreshold field leakage. In addition, the subthreshold leakage current between the two diffusions on the test structures increased as a function of stress voltage and time - similar to the failing signature of the actual SRAM. The mechanism responsible for the latent increase in leakage current is believed to be electron trapping near the drain end of the parasitic field device. Improvement of the transistor isolation properties was achieved through process modifications and subsequently the failure mechanism was eliminated