When one department performs extensive analysis, the need for common data within a database structure may be required. A realistic paperless database was developed to solve department needs. This database is carried out with the combination of a Client Module, Operation Module and Management Module. The Client Module includes on-line request for analysis, intensive query, retrieval of the analysis result with digital image and image processing. The Operation Module provides real-time digital data acquisition from the analysis equipment, which have the data types of image, text or graph and real-time data transmission to a dedicated server Digital Alpha 4100. The Management Module includes approval of the request for analysis from the Client Module, creation of reports about analysis results and statistical service for the subjects like failure modes in a device, operation time of equipment and so on. These modules allow multi-users to access the database through the Web on the Intranet. Our database can be also linked to the in-line database and the failure analysis with DRT SEM and physical analysis can become more effective with the use of in-line inspection data. This paper presents the framework of the database along with a technical description of the database implementation.

In the process of fabricating high density mounting boards, locating faults in boards rejected in a functional test requires special circuit knowledge and skills, so it has been becoming more and more difficult to find the faults in a limited time. To address this problem, we have developed an Auto-Fault-Locating-System for mounting boards using a simple comparison technique and faulty net tracing algorithm. In the system, net-propagated faults are detected by comparing pulse-counts and voltages in good boards and faulty ones under full power supply. Faulty nets, which include the fault origin, are detected by tracing backward via a faulty propagation path using the input-output attribute of terminals. Measurements require 2.5 seconds per net (i.e., about 40 minutes for 1,000 nets), and searching faulty nets requires 10-20 seconds. The system successfully located the fault origin in 22 out of 25 boards rejected in a functional test. The located fault origins were found to be IC problems, pattern errors, open terminals and shorts between nets.

Recent progress with IDDQ testing has demonstrated the ability to identify a majority of defects in logic ICs. IDDQ testing has also been integrated in fault simulators embedded with automatic test pattern generation (ATPG) algorithms to further extend defect coverage. However, this progress has not eliminated the complex task of defect localization on the silicon level of ICs. To deal with the challenge of faster and more accurate defect localization with greater sensitivity, we have developed a new method based on voltage contrast capabilities for internal localization of IDDQ defects. This method covers an extended range of cases: functional or non functional devices, with or without CAD information, etc... Using only the same test pattern as that used to identify a faulty circuit, the equipotential line of the failure can be located. This approach can also be extended to coupling with netlist information. For example, the equipotential line previously found on the faulty circuit can be compared with the fault simulator output. Then, the site of the simulated defect corresponding to the physical failure can be extracted and local deprocessing with a FIB can be used on the failed circuit to physically reveal the defect with an improved turn around time.

The dependence of a defective device's voltage-current characteristics on temperature is studied, both from a theoretical perspective and through a series of actual case studies. The shape of the current vs. temperature curve is shown to be a good prognosticator of the defect type, and as such a valuable complement to other non-destructive defect characterization techniques such as photoemission spectrum analysis [1].

Internal IC probing has become an important tool for failure analysis and defect localization. Optical stimulation of logical transients enables the investigation of electrical pulse propagation through IC-regions which are not directly connected to an external input. The signal detection should be as directly as possible to avoid misinterpretation of experimental results, especially for time-resolved measurements. This paper describes the implementation of a capacitive coupling technique on a laser scanning microscope and on a needle prober. Results of static and time-resolved measurements are presented and compared to those obtained by OBIC measurements.

A commercial Electron-beam measurement set-up has been applied to study triggering and turn-on of NMOS ESD protection transistors. Using this technique turn-on times in the sub halve nanosecond range could be determined for the first time. The measured transient behaviour could be described accurately using SPICE simulations. The measurements have been used to explain the CDM failure mode characteristics of the NMOS protection transistor.

Conventional needle probecard techniques suffer from several problems: needles scratch the pads causing bonding problems, the maximum test speed is limited by the poor high frequency performance of the needle contacts. This contribution presents a new contactless method to inject test stimuli and to monitor the output. On chip photo diodes and simple receiver circuits transform light pulses to proper input signals, while a capacitively coupled probe with a very sensitive charge amplifier detects the output signal. The apparational overhead to conventional test system is small as well as the chip space required for photo diode and receiver circuit.