High volume products in manufacturing require fast yield learning, root cause identification, and verification that process or tool problems are fixed. Yield losses of 1% correspond to very large dollar losses. Therefore, it is important to have sophisticated data analysis tools that handle large volumes of data to drive higher yields. This paper will present our methodology for defining yields, assessing wafer yield signatures, and using data analysis tools to determine tools or processes which drive yield loss. A SAS based data analysis tool will be shown which can identify tool or process related problems causing abnormalities in parametrics and impacting yield. Case studies illustrating the usefulness of the tool are shown for a Synchronous Dynamic Random Access Memory (SDRAM) product from our wafer fab. In the final analysis, it is clear that an efficient data analysis approach utilizes resources most effectively and pinpoints yield problems with minimal cycle time.

In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

The advances made in process technology along with system-on-a-chip capabilities have made failure analysis ever more difficult and expensive to perform. Quick product time-to-market and the required high fabrication yields demand top quality performance from the failure analysis team. In this paper we present a methodology for embedded memory analysis (EMA) which provides design, layout, and process characterization, and yield and reliability enhancement for standard cell ASIC products. The methodology takes the power of memory testing and failure signature analysis and brings it to the logic chip to accurately predict root cause defects. We also present the application tool that is used to query, bitmap, analyze, and report the data, along with numerous case histories. This process has greatly improved failure analysis hit rates and provided much quicker turn-times for process improvement feedback and customer return root cause analysis.

This paper illustrates a yield enhancement effort on a Digital Signal Processor (DSP) where random columns in the Static Random Access Memory (SRAM) were found to be failing. In this SRAM circuit, sense amps are designed with a two-stage separation and latch sequence. In the failing devices the bit line and bit_bar line were not separated far enough in voltage before latching got triggered. The design team determined that the sense amp was being turned on too quickly. The final conclusion was that a marginal sense amp design, combined with process deviations, would result in this type of failure. The possible process issues were narrowed to variations of via resistances on the bit and bit_bar lines. Scanning Electron Microscope (SEM) inspection of the the Focused Ion Beam (FIB) cross sections followed by Transmission Electron Microscopy (TEM) showed the presence of contaminants at the bottom of the vias causing resistance variations.

Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.