In this paper, the development of advanced emission data analysis methodologies for IC debugging and characterization is discussed. Techniques for automated layout to emission registration and data segmentations are proposed and demonstrated using both 22 nm and 14 nm SOI test chips. In particular, gate level registration accuracy is leveraged to compare the emission of different types of gates and quickly create variability maps automatically.

Laser voltage probing (LVP) has been extensively used for fault isolation over the last decade; however fault isolation in practice primarily relies on good-to-bad comparisons. In the case of complex logic failures at advanced technology nodes, understanding the components of the measured data can improve accuracy and speed of fault isolation. This work demonstrates the use of second harmonic and thermal effects of LVP to improve fault isolation with specific examples. In the first case, second harmonic frequency is used to identify duty cycle degradation. Monitoring the relative amplitude of the second harmonic helps identify minute deviations in the duty cycle with a scan over a region, as opposed to collecting multiple high resolution waveforms at each node. This can be used to identify timing degradation such as signal slope variation as well. In the second example, identifying abnormal data at the failing device as temperature dependent effect helps refine the fault isolation further.

In this paper, the effects of an open defect resulting in floating gate on combinational logic gate structures are studied. From this study, a novel method is derived to predict and narrow down the potential open defect location from a long failure path that is driving multiple branches of input nodes, into a much smaller segment without EBAC analysis. This method is applied with great success to localize open defects on actual low yield cases from advanced technology nodes with significant reduction in FA cycle time.

Time-resolved laser assisted device alteration (TR-LADA) has interesting applications to reduce the spatial spread of LADA site, as well as benefit device design debug. This paper describes an implementation using a 1063nm wavelength nanosecond pulse-on-demand laser diode to obtain a timing resolution of 1-2 tester cycles and spatial resolution enhancements to LADA sites. We also present potential capabilities of TR-LADA in the debug of analog circuitry.

Applications of MpOBIC (Multi-photon Optical Beam Induced Current) are discussed for use in defect localization. The MpOBIC signals in a ring oscillator under static conditions are examined and demonstrate the superior optical resolution of the system over traditional OBIRCH. A 5-fin diode test structure is examined under passive conditions, demonstrating that true multi-photon OBIC has occurred from the backside. The same diode is examined in forward bias, and the resulting discussion concludes that both OBIC and OBIRCH signals are present in the sample. Thus, we claim that both OBIC and OBIRCH signals can provide device characterization information from an MpOBIC system.

This paper proves the effects of laser pulse width on the lowering of LADA and SEU threshold laser energy. The soft failure rate is found to increase with reducing pulse widths from 100 μs to 2 μs. The results obtained suggest that pulsed-LADA for soft defect characterization and localization could offer notably improved SNR and turnaround time. This is because it is no longer critical to assign the test point close to the shmoo boundary which is well known to give rise to spurious signals. With a less noisy signal image, the overall debug cycle time can be shortened since multiple frames average is not required. Further driven by the motivation to seek a viable alternative to overcome the challenge of weak LADA signals due to poor transmittance of 1064 nm wavelength laser through full wafer thickness and a solid immersion lens, preliminary results based on 1122 nm wavelength laser is also presented. It is observed that though the OBIC quantum efficiency at 1122 nm is 80% lower than at 1064 nm, it is 25% higher when a solid immersion lens is used.

EeLADA has been introduced previously as a prospective alternative approach to DFT scan diagnosis for scan logic defect localization. It has the capability to reveal induced signals from laser stimulation that are relevant to the failure signature by comparing failing pins and cycles of the bad device. Multiple schemes involving different combinations for comparison are possible. Defect simulations based on cell fault injections on a multi-level logic of a real digital device circuit characterizes the different comparison schemes. The findings are used to devise an optimized methodology to determine suspected fail locations to guide physical failure analysis to reveal the defect. A successful case study substantiates the method.

This work investigates the origin of the single event hard failures of an advanced commercial FinFET microprocessor induced by heavy ions using a combination of failure analysis tools. It focuses on elucidating the reason behind the hard and catastrophic failures of Intel 5th Generation MCP Broadwell microprocessors due to exposure to ionizing radiation. The failure analysis techniques point toward the same area on the platform control hub (PCH) die. Contrary to the initial (intuitive) hypothesis, the hard failures observed in the Intel 5th Generation MCP Broadwell are caused by 32-nm planar PCH die. These failures do not seem to be anyhow related to the FinFET technology, but the exact physical mechanism has yet to be identified. In conclusion, no critical issues or showstoppers were observed during heavy ion testing of Intel 14-nm Tri-Gate FinFET commercial microprocessors, which would prevent these devices from being considered as future space candidate parts.

In most of the non-destructive electrical fault isolation cases, techniques such as DLS, Photon Emission, LIT, OBIRCH indicate a fault location directly. But relying on just one of these techniques for marginal failure mechanism is not enough for better fault localization. When Failure Analysis (FA) engineers encounter high NDF (No Defect Found) rates, by using only one of the techniques, they may need to consider the relationship between the responded locations by different techniques and fail phenomenon for better defect isolation. This paper talks about how a responded DLS location does not always indicate a fault location and how LVP data collected using DLS location can pin point the real defect location.

Through custom test pattern generation and SRAM design analysis, we present the first demonstration of Laser Voltage Imaging (LVI) and Probing (LVP) for the successful fault isolation and physical analysis of DQ failures within a 14nm SRAM macro. These findings revealed the fail site to reside within the I/O circuitry of the associated failing pin, a previously overlooked location as common block failures are typically associated with physical anomalies within the SRAM periphery.

This paper presents the successful use of the novel inline product-like logic vehicle (PATO) during the last technology development phases of IBM's 22nm SOI technology node. It provides information on the sequential PATO inline test flow, commonality analysis procedure, and commonality signature trending. The paper presents examples of systematic defects uniquely captured by the product-like back end of the line layout. Moreover, this complex logic vehicle also uncovered a rich Pareto of more than 20 types of systematic and random defect mechanisms across the front end of the line, the middle end of the line, and the back end of the line. And more importantly, the non-defect found rate was kept below 20%. This achievement was possible by: leveraging high volume inline test ATPG scan fail data through the novel commonality analysis approach; and selecting the highest ATPG confidence defects representing a known commonality signature to physical failure analysis.

Wafer level tester-based fault isolation (FI) tool exists back in 2008 but is not widely adopted by industry. This is expected because such tool is commonly known for its primary role in dynamic electrical FI. Since packages are readily available, there is little motivation in using wafers. This paper provides a different perspective to consider such tool as part of a wafer level debug solution to enhance current failure pre diagnostic and diagnosis capabilities, to meet requirements for fast and effective yield ramp. Test cases are presented to support this perspective and a roadmap that guides next generation wafer level FI tool is also proposed at the end of the paper.

This paper describes a new approach for quickly ramping up the yield for new CMOS technologies by performing a cell-internal (CI) diagnosis based on the cell-aware (CA) methodology. We present results from carrying out this new method on a test chip of a 28-nm technology. After creating defect-oriented CA test patterns for this test chip, we tested various wafers with those CA patterns, selected fail data, conducted a normal electrical failure analysis, and used the new CI diagnosis method to guide the physical failure analysis (PFA) process to look specifically for hot-spot areas within standard library cells. This new approach can reduce the yield ramp-up time significantly.

The root cause deconvolution (RCD) provides an easy-to-understand defect Pareto, together with targeted physical failure analysis candidates. Unfortunately, even the RCD analysis also has some assumptions and limitations, and its result cannot always be interpreted literally. This calls for a variety of conventional yield analysis techniques to be adopted in parallel to improve the confidence in the RCD results. This paper briefly introduces the RCD analysis and explains how it distinguishes itself from other conventional volume diagnosis analysis techniques. Its typical inputs and outputs are discussed as well. Next, the paper focuses on two case studies where the authors leverage RCD for logic yield improvement together with other conventional analysis techniques. It then proposes a comprehensive analysis system that is backed up by accumulating RCD results over time and across different design IPs.

In this paper the new Vion™ Plasma-FIB system, developed by FEI, is evaluated for cross sectioning of Cu filled Through Silicon Via (TSV) interconnects. The aim of the study presented in this paper is to evaluate and optimise different Plasma-FIB (P-FIB) milling strategies in terms of performance and cross section surface quality. The sufficient preservation of microstructures within cross sections is crucial for subsequent Electron Backscatter Diffraction (EBSD) grain structure analyses and a high resolution interface characterisation by TEM.

Microstructure and its effect on mechanical behavior of ultrafine interconnects have been studied in this paper using a modeling approach. The microstructure from the processes of solidification, spinodal decomposition, and grain growth in ultrafine interconnects has highlighted its importance. The size, geometry and composition of interconnects as well as the elastic energy can influence microstructure and thus the mechanical behavior. Quantification of microstructure in ultrafine interconnects is a necessary step to establish the linkage between microstructure and reliability.

As the TSV count increases, chip yield can be severely degraded due to failures during the TSV or die-stacking processes. This paper will present and discuss on the usage of failure masks designed to detect and differentiate failure types such as connection failure and insulator failure based on frequency-domain one point probing measurement. The failure masks are proposed on the basis of the frequency domain analysis of TSV failures with Z11 magnitudes.

In this paper different methods and novel tools for failure localisation and high resolution material analysis for open TSV interconnects will be discussed. The paper shows the application of enhanced methods for the localisation of sidewall shorts in open TSV structures by adapted Photoemission Microscopy (PEM), Lock-in Thermography (LIT) and Electron Beam Absorbed Imaging (EBAC). In addition, a new highly efficient target preparation technique is presented, which allows the combination of Laser and FIB milling, in order to access TSV sidewall defects. Finally the use of this technique is demonstrated in a failure analysis case study.

Lock-in thermography and magnetic current imaging are emerging as the two image-based fault isolation methods most capable of meeting the challenges of short and open defect localization in thick, opaque assemblies. Such devices are rapidly becoming prevalent as 3D integration begins to ramp up production. This paper expands on previously published work with a qualitative comparison of the techniques on single chip and stacked die packages with known designed-in or FIB created defects.

The 3D package configuration presents challenges to conventional Fault Isolation (FI) and Failure Analysis (FA) methods. This paper illustrates that with correct Electro Optical Terahertz Pulse Reflectometry (EOTPR) data processing, interpretation and additional reference spectra, the combination of EOTPR to isolate the open/high resistance failure location and 3D X-ray Computed Tomography (CT) to image the failure is very effective for System in a Package (SIP) FI/FA.