Yield analysis of sub-micron devices is an ever-increasing challenge. The difficulty is compounded by the lack of in-line inspection data as many companies adopt foundry or fab-less models for acquiring wafers. In this scenario, failure analysis is increasingly critical to help drive yields. Failure analysis is a process of fault isolation, or a method of isolating failures as precisely as possible followed by identification of a physical defect. As the number of transistors and metal layers increase, traditional fault isolation techniques are less successful at isolating a cause of failures. Costs are increasing due to the amount of time needed to locate the physical defect. One solution to the yield analysis problem is scan diagnosis based fault isolation. Previous scan diagnosis based techniques were limited with little information about the type of fault and confidence of diagnosis. With new scan diagnosis algorithms it is now possible to not only isolate, but to identify the type of fault as well as assigning a confidence ranking prior to any destructive analysis. This paper presents multiple case studies illustrating the application of scan diagnosis as an effective means to achieve yield enhancement. The advanced scan diagnostic tool used in this study provides information about the fault type as well as fault location. This information focuses failure analysis efforts toward a suspected defect, decreasing the cycle time required to determine root cause, as well as increasing the over all success rate.

Precise isolation and resolution of scan chain defects are more critical than ever due to increased reliance on scan-based design to achieve desired test content. At the same time, its diagnosis is becoming more difficult as product design increases in complexity alongside shrinking fabrication processes. In this paper, we present a new scan chain diagnosis procedure that is centered on Load Pass Unload Fail/Load Fail Unload Pass (LPUF/LFUP) and Scan Shift Logic State Mapping (SSLSM) techniques to isolate both stuck-at and timing scan chain faults without the design overhead and defect assumptions of previously proposed methods. More importantly, this procedure is extended to analyze scan chain with multiple defects, which is becoming a more frequent occurrence as process scales down in size.

Due to the development of smaller and denser manufacturing processes most of the hardware localization techniques cannot keep up satisfactorily with the technology trend. There is an increased need in precise and accurate software based diagnosis tools to help identify the fault location. This paper describes the software based fault diagnosis method used within Philips, focusing on the features developed to increase its accuracy.

Light Emission due to Off-State Leakage Current (LEOSLC) is used in combination with the Picosecond Imaging Circuit Analysis (PICA) method to effectively diagnose and localize defects in a broken scan chain. As usual, the emission base method shows to be very effective in debugging the problem; the defect is successfully identified by the optical technique and confirmed by Physical Failure Analysis (PFA).

The power supply transient/quiescent signal (IDDT/IDDQ) methods that we propose for defect localization analyze regional signal variations introduced by defects at a set of power supply ports on the chip under test (CUT). The methods are based on the comparison of the CUT with a golden reference chip, either simulated or determined to be defect-free, with the objective of distinguishing anomalous signal behavior introduced by a defect from that introduced by process variations. However, variations in contact resistance between the probe card and the CUT introduces anomalies in the measured power supply signals that complicates the task of comparing data between chips. This paper presents hardware results that demonstrate the effectiveness of a previously developed calibration technique designed to eliminate these types of signal anomalies introduced by the testing environment. The CUT hardware data presented in this work is calibrated using simulations of the CUT’s power grid and special on-chip sources of stimuli called ‘calibration circuits’. Several novel Look-Up Table based defect localization techniques are proposed that analyze the calibrated power supplies signals. The results of predicting the locations of emulated defects in nine copies of a test chip demonstrate the effectiveness of the techniques.

Precise fail site isolation plays a very important role today in the world of semiconductors. Its importance increases more, as the devices are of cutting edge technology with increasing complexity and decreasing dimensions. Global fail site isolations techniques (like XIVA, Photo Emission, FMI etc) and tester based techniques (using automatic test equipment, Fastscan etc) alone, are no longer sufficient and may not be successful. Long net lists and large fail sites isolated by these methods pose problems for physical failure analysis. Planarity of these large areas during parallel lap and inspection times using the SEM is difficult and tedious, thus leading to long cycle times and low resolution rates. There exists a need for precise fail site isolation. In many cases, no single technique can be used to narrow down a fail site significantly. Instead a combination of different techniques must be used. In this paper we present a case study, where a combination of complimentary techniques are used to successfully isolate a fail area of more than 1300 microns in length to less than 100 microns on a single failing net.

The continually increasing complexity of integrated circuits has made fault localization progressively more difficult. Despite significant imp rovements in test and diagnosis tools, probing is still required for acquiring new information and for confirming test results. For this reason, we have developed an optimized diagnosis -to-probing flow which significantly reduces the number of nodes to be probed and which dramatically cuts the cost of fault localization. With this approach, probing can be integrated in test and diagnosis operations to reach nodes which are known to be untestable.

Since failure analysis (FA) tools originated in the design-for-test (DFT) realm, most have abstractions that reflect a designer's viewpoint. These abstractions prevent easy application of diagnosis results in the physical world of the FA lab. This article presents a fault diagnosis system, DFS/FA, which bridges the DFT and FA worlds. First, it describes the motivation for building DFS/FA and how it is an improvement over off-the-shelf tools and explains the DFS/FA building blocks on which the diagnosis tool depends. The article then discusses the diagnosis algorithm in detail and provides an overview of some of the supporting tools that make DFS/FA a complete solution for FA. It also presents a FA example where DFS/FA has been applied. The example demonstrates how the consideration of physical proximity improves the accuracy without sacrificing precision.

In this paper, DACS stands for Defects that Affect Chain and System, which could be any type of silicon defects caused by an unintentional interaction between a scan chain signal and a system logic signal. The device could fail scan chain testing or show up as a latent failure in the customer’s system. A novel diagnosis methodology is proposed to locate both ends of a DACS. The proposed algorithm can be generally applied to any type of DACS. Experimental results on industrial chips demonstrate the effectiveness of the proposed method.

Building a portfolio of deformations is the key step for building better defect models for the test and yield learning domain. A viable approach to achieve this goal is through geometric characterization and classification of failure patterns found on memory fail bitmaps. In this paper, we present preliminary results on how to build such a portfolio of deformations for an IC technology of interest based on a fail bitmap analysis study conducted on large, modern SRAM memory products.

A single cell failure (SCF) is a common fail signature in dynamic random access memories (DRAMs). Generally write and read problems can be observed if a cell capacitor is not connected properly to its bitline. If the critical resistance of this connection exceeds a given threshold a failure might occur. In this analysis this threshold can be varied by a lateral gate effect of neighboring trenches. The first section gives a short introduction to the problem. An experimental analysis follows in the second section. Simulation results are presented in the third part and a short summary is given at the end.

Designing devices for failure analisys (FA) is becoming increasingly critical as structure geometries and killer defects rapidly decrease in size. Naturally, devices that are designed for FA are much easier to analyze and have a higher FA success rate than those that are not. Several analyses of functional failures in a 0.18um CMOS SRAM are presented in this paper to demonstrate “Design For FA” usefulness and application. Physical analysis methodology is also discussed.

Parametric analysis of microprocessor SRAM through special design for test features (DFT) is used extensively by fault isolation and failure analysis engineers to find and characterize defects. While regular raster and special cache patterns (i.e. weak-write test mode) detect many stuck-at faults, a parametric analysis is needed to identify which defect mechanism is the cause of a cache failure. Pico-probing is the most common method of parametric analysis on SRAM cells, but is becoming increasingly difficult on smaller geometries. These curves can also be taken non-destructively by muxing any bitline (BL) and bitline_bar (BL#) of an internal cache to an I/O pin and sweeping these pins with an external PMU (a test mode known as low yield analysis, or LYA). Unfortunately, a growing amount of leakage on each new process is distorting these LYA testmode I-V curves, making it increasingly difficult to find and differentiate defects. The goal of this paper is to discuss the simulation and silicon results of a concept On-Die LYA (ODLYA) circuit implemented in a 65 nm CMOS process technology. ODLYA is used to curve-trace individual transistors within an SRAM cell and read out results in an automated fashion. Taking measurements on-die eliminates interconnect-dominated IR drop and leakage distortion from several levels of multiplexing. The proposed implementation enables non-destructive high-speed parametric analysis with less dependency on growing cache sizes, number of cores, and scaling process technologies.

This paper proposes a taxonomy of process-induced deformations of IC structures. Such a taxonomy is envisioned as a foundation for yield modeling and development of test strategies, as well as, for design of ICs with redundancy. It is proposed to address the rapidly growing complexity of interaction between process-induced deformations of IC structures and steadily shrinking geometry of deep submicron ICs.

SRAM bit fail maps (BFM) are routinely collected during earlier phases of yield ramping, providing a rich source of information for IC failure and deformation learning. In this paper, we present an automated approach to analyzing BFM data efficiently. We also demonstrate the usability of our analysis framework using real BFM test data from a large, modern SRAM test vehicle.

A common failure signature in dynamic random access memories (DRAMs) is the single cell failure. The charge is lost and thereby the information stored in trench capacitors can be destroyed by high resistive leakage paths. The nature of the leakage path determines the properties of the failure such as temperature-, voltage- and timing-dependencies and its stability. In this study, high resistive leakage paths were investigated and delimited from classical shorts by estimating the order of magnitude of the leakage current and by comparison to a simple resistive leakage path. Such an investigation is the basis for a defect-based test approach that leads to multiparameter tests [1]. An introduction to the problem is given in the first section, while the second section deals with the characterization of the defects in two case studies. A short summary is given in the end.

The semiconductor industry’s efforts to integrate dielectrics into Si devices has driven characterization efforts to address the challenges presented by adoption of this new class of materials. Abundant literature exists on the considerations required for CMP process recommendations for successful fabrication, adhesion requirements for both fabrication and assembly, and considerations for interconnect structure to enable wire-bonding. There is also interest in understanding the wafer level test challenges presented by the low-K devices. In addition to the typical concerns about reaching the best compromise of good contact resistance (CRES) performance with a minimum amount of probe damage, low-K materials present an increased risk of compromising the dielectric or barrier layers beneath bond pads. For a better understanding of the dynamic contact phenomenon of probing and its effect on the integrated circuit (IC) metal stack, a specialized in-situ nanomanipulator tool was developed for simultaneous visualization of probing events with data recording of electrical and load measurements. This paper describes initial research with this new tool.

We present a generalized method to attack fault diagnosis at the logic level that aims at localizing and differentiating fault types. In particular, we present an application of this method that aids in distinguishing opens and two-line shorts. While past work has addressed distinction between shorts and opens, we present an algorithm to generate more test patterns to narrow down the diagnosis callout based on type or location. In general, we are not limited to a few fault models as our description of the logic misbehavior is built on fault tuples. This becomes important in the area of fault and defect characterization. Results based on logic validation and SPICE simulations of extracted netlists indicate the usefulness and efficiency of our approach.

Power supply noise (PSN) is becoming more severe as technology scales, and can cause signal distortion and increase gate delay. This can further result in improper circuit operation. In this paper, we propose a novel approach based on ATE (automatic test equipment) that teaches neural networks (NN) to correctly classify a set of worst case input patterns with respect to the maximum instantaneous current. This can be thought of as a learning behavior of chip power consumption change due to different input patterns. Then a genetic algorithm (GA) was applied to further optimize this set of NN worst case patterns. A final set of worst case patterns were expected to detect a small critical sequence of high switching currents that was directly related to the worst case power supply noise. This novel diagnosis approach can efficiently identify the defective design or weakness due to PSN as well as locate the defect or weaknesses within the design.

The subject of this paper is statistical post-processing of wafer-sort test data. Statistical post-processing (SPP) has successfully separated many of the effects of defects from normal wafer-to-wafer variation. The data-driven method is used with parametric data such as IDDQ, minVDD, and others. The neighboring die are used to form an estimate of a die’s expected value. The resulting SPP residual has smaller variance than the original measurement variance and filters most of the spatial patterns that obscure data outliers from normal variation. The method is applicable to a wide variety of process parameter variation issues of concern to both test and FA communities.