Passive voltage contrast (PVC) is a conventional technique for open contact isolation. However PVC application is limited as it just can tell whether contact is grounded or floating [1]. In this work primary current and voltage adjustment criterion is developed to break through this limitation. Adjusting the electron acceleration voltage (EPE) or current value can enhance differential voltage contrast effect. Hence, isolation of thin gate oxide leakage and N+/PW junction leakage can be distinguished in both contacts and metals. Voltage contrast (VC) image under varying primary current and voltage is demonstrated experimentally and discussed.

Infrared Micro Thermography can be applied as electrical fault identification in situations where photon emission is ineffective. Defects, such as certain types of stringers and particles, may conduct without emitting photons in the visible range. Arrayed infrared sensors such as an InSb 512x512 detector, coupled with the appropriate infrared optics can image the heat generated from the leakage site. Heating on the order of a fraction of a degree Kelvin can be observed. The heat signature can be superimposed on a normal optical image of the chip. Several practical examples using this fault identification technique are described.

With gate oxide thickness getting thinner and thinner, the possibility of pinholes, thickness variations, and surface irregularity is greatly increasing. Gate oxide integrity (GOI) tests are done to ensure product quality and uniformity of the gate oxide layer. Five percent (5%) Choline OH is normally used to remove bulk silicon in backside analysis, but oftentimes if gate oxide punch through is not the cause of the failure, further layer analysis of the sample is extremely difficult and sometimes impossible. When samples fail due to current leakage it most often means that a photoemission is given off and can be detected for defect localization. But not all devices that fail due to current leakage are caused by gate oxide punch through. Metal bridging or contact interface contaminates can often be the root cause of the failure. Sample de-layering is the only way to find such defects, so backside bulk silicon removal would not be appropriate. Many times when there is a problem with the gate oxide, punch through or pinhole, the size of the hole would be very useful information. Heated KOH is often used to remove poly silicon but it etches so rapidly that the silicon substrate is often over etched and the gate oxide is destroyed leaving a large square hole. Choline OH is a slow selective etch that can be controlled very easily and does not damage the oxide.

This paper describes a novel method of sample preparation for Transmission Electron Microscope (TEM) analysis, particularly a technique for photoresist sample preparation for TEM analysis. In the analysis of an ultra large scale integrated (ULSI) circuit, the profile images of a ULSI circuit sample are crucial. In order to identify the tiny features of modern semiconductor devices clearly, TEMs are used because of their high spatial resolution. However, TEM analysis is not available for photoresist material, especially for a patterned photoresist layer, due to the difficulty in specimen preparation and its susceptibility to electron beam damage during TEM analysis. A critical step in preparing this type of TEM specimens is to deposit a conductive layer and a dielectric layer upon the patterned phototresist by a physical vapor deposition process at room temperature first, then followed by a focus ion beam (FIB) process. The exact profile of the patterned photoresist is kept, during specimen preparation and TEM analysis, by this modified method. Precise dimension measurements are then possible.

OBIRCH (Optical Beam Induced Resistivity Change) has been developed to an industrial useable equipment for failure localization. The method turned out to be in certain manner complementary to emission microscopy, detecting failures mainly related to metal wiring problems. At EMPA, EM Microelectronic Marin and CNES Toulouse, first experiences have been collected with this method, using external and CNES-owned OBIRCH equipment. It turned out, that the method does not only help to localize functional failures, but is also most suitable as a reliability-related failure detection tool: OBIRCH-indicates signals at positions where no electrical failure could be seen in standard electrical testing. Analyzing those positions physically, it turned out that indeed significant failure textures have been found, which, however, did not show up electrically, yet. On the other hand, application of OBIRCH on functional devices shows some severe limitations. Thus, OBIRCH might become an interesting in-line tool of the future to detect and to screen reliability-critical failure types, which would pass all present electrical in-line testing on PCMs (Process Control Monitor structures).

Focused ion beam (FIB) techniques are continuously improved to meet the demands of shrinking device dimensions and new technologies. We developed a simultaneous milling and deposition FIB technique to provide electrical contact to small buried targets in semiconductors. This method is applied to directly connect the deep trench (DT) capacitor of a DRAM single cell in deep submicron technology. By carefully adjusting the deposition parameters (scanned area < (0.3 µm)2, beam current < 20 pA) we are able to influence diameter, depth and Pt fill properties of the hole to meet the very restricted requirements for successful DT connection (hole diameter < 200 nm at DT level). Electrical measurements are performed on DRAM single cells after connecting buried plate (n-band), p-well, wordline, bitline and DT. The probe pads were Pt, deposited with ion beam assistance, on top of highly insulating SiOx, deposited with electron beam assistance by using a dualbeam FIB. The read and write conditions of an active memory cell are studied. The presented method increases the capabilities to localize and characterize trench related failure mechanisms.

Determination of metal bridging failures on plastic encapsulated devices is difficult due to the metal etching effects that occur while removing many of the plastic mold compounds. Typically, the acids used to remove the encapsulation are corrosive to the metals that are found within the device. Thus, decapsulation can result in removal of the failure mechanism. Mechanical techniques are often not successful due to damage that results in destruction of the die and failure mechanism. This paper discusses a novel approach to these types of failures using a silicon etch and a backside evaluation. The desirable characteristics of the technique would be to remove the silicon and leave typical device metals unaffected. It would also be preferable that the device passivation and oxides not be etched so that the failure location is not disturbed. The use of Tetramethylammonium Hydroxide (TMAH), was found to fit these prerequisites. The technique was tested on clip attached Schottky diodes that exhibited resistive shorting. The use of the TMAH technique was successful at exposing thin solder bridges that extruded over the edge of the die resulting in failure.

A new Au etch, recently developed for selective Au etching on Ti/Pt/Au metallization of optoelectronic devices, has been tested on Au wires bonded on Al films. Contrary to theoretical expectations, Au wires are removed without Al damage, except for a very localized area around the bond interface. The role of the native Al oxide is discussed in preserving Al and allowing Au lift off.

A novel method has been developed to reveal the entire three dimensional (3D) deep trench (DT) capacitors for inspection in DRAM, especially NO capacitor dielectrics, ASG residues at corners, morphology etc., for process evaluation and failure analysis. It offers an alternative to conventional cross-section polishing, top down polishing or FIB milling methods. A DRAM chip was ground and polished down to a certain level from the chip backside. An etching solution was then applied to enhance the DTs appearance. 3D DTs can be inspected in scanning electron microscopy (SEM). The entire DTs or specific DT also can be lifted out for detailed investigation in transmission electron microscopy (TEM). The innovation of this technique is to provide a quick 3D observation in SEM, and much more flexibility to an entire DT inspection in TEM, which were not presented before.

The focused ion beam system (FIB) has become a valuable tool for the preparation of transmission electron microscope (TEM) samples. Several FIB preparation techniques exist but of particular interest is the lift-out technique, which allows for the extraction of a thin membrane from a bulk material. This technique has seen great success in the preparation of cross sectional samples. We explore the use of this technique for planar sample preparation to examine grain deformation due to nanoindentation in a reference copper material.

Die cracking is one of the primary failure areas in semiconductor manufacturing and in product longevity. Often die cracking emanates from stress concentrations formed on chips during the dicing process. In order to properly characterize and analyze die cracking relating to the dicing process, we must first properly and accurately quantify and characterize the dicing process. This paper describes the methodology to perform this first step in a premier fashion. In the past, quantification of the dicing process has been a manual operation usually under a microscope. Now there is a new state-of-the-art metrology tool (KIS2010 Inspection System) for quantifying all parameters associated with the dicing process. The system provides computer controlled robotic inspection combined with onboard statistical data reduction software to display results. The goal of this paper is to provide other engineers working in defect and failure analysis an insight into the power of this metrology tool and how it can provide a firm basis for characterizing failures related to the dicing process.

This paper presents a new automatic die positioning system for failure analysis work in the scanning electron microscope (SEM). The system makes use of machine vision to automatically locate a prespecified failure site on an integrated circuit (IC) sample, without the need for a high-accuracy specimen stage or modifications to existing SEM hardware. Depending on the appearance of the desired failure site, either image registration or feature tracking is used to locate the site. To locate failure sites containing unique and distinguishing features, such as those found on logic ICs, an image registration procedure is used. Experiments carried out on a microprocessor and an analogue-to-digital converter show that the new system is able to accurately locate the failure site, even in the presence of IC sample rotation and image scaling. Moreover, the accuracy of the technique has been shown to be independent of the complexity and minimum feature size of the sample used. To locate failure sites containing repetitive IC patterns, such as those from DRAM samples, a feature tracking approach was incorporated into the original die positioning algorithm. The final system can therefore locate many types of failure sites, regardless of whether they have unique features or repetitive IC patterns.

Single probe beam phase-sensitive detection has been applied to backside optical probing using an interferometer with a novel vibration cancellation scheme. Improved waveform quality and consistency, compared to amplitude-sensitive detection, has been successfully demonstrated on a number of CMOS microprocessors based on the 0.18 um logic process technology. The interferometric probing scheme will be described in detail and results will be presented.

Analysis of manufacturing data as a tool for failure analysts often meets with roadblocks due to the complex non-linear behaviors of the relationships between failure rates and explanatory variables drawn from process history. The current work describes how the use of a comprehensive engineering database and data mining technology over-comes some of these difficulties and enables new classes of problems to be solved. The characteristics of the database design necessary for adequate data coverage and unit traceability are discussed. Data mining technology is explained and contrasted with traditional statistical approaches as well as those of expert systems, neural nets, and signature analysis. Data mining is applied to a number of common problem scenarios. Finally, future trends in data mining technology relevant to failure analysis are discussed.

This paper describes a method for applying passive voltage contrast (PVC) in the failure analysis of CMOS LSIs using a conventional scanning electron microscope (SEM), and demonstrates the effectiveness of this method. It was confirmed by measurement of the stage absorption current that the combined emission efficiency of secondary and backscattered electrons from aluminum is larger than 1 at acceleration voltages lower than about 2.5 kV. This means that local positive charges should be generated on a conductor in association with its irradiation with an electron beam at a relatively low acceleration voltage. However, a pn junction connected to the conductor would change the potential. The potential is still positive if the conductor is connected to a reverse-biased diode but becomes lower if such a diode is forward-biased. The PVC signal observed on the conductor should be defined according to the bias state of any diode connected to the conductor. Therefore, for failure analysis applications, if the bias state of a diode connected to a suspicious conductor is known, the PVC observation is useful for determining whether there is an open defect or a short-circuit defect. Some case studies are presented to demonstrate the effectiveness of the method. Cross-sectional TEM observations of defects localized in this way are also included.

IDDQ testing detects a majority of faults in logic ICs. To improve defect coverage with very short test patterns, IDDQ testing has been integrated in fault simulators embedded with automatic test pattern generation (ATPG) algorithms. Nevertheless, for failure analysis purposes, this progress has not eliminated the complex task of fault isolation at the silicon level of ICs. Defect localization is facilitated with IDDQ testing because the defect is detected as soon as it is activated inside the device. At the failed vector, abnormal IDDQ current is measured and accurate localization of the corresponding defect inside the chip can be performed. Thermally related techniques or emission microscopy can be used for this localization process. Very powerful tools like electron beam testers can also be used to deeply analyze faulty devices by internal contactless testing. In this paper, we will present an application of IDDQ testing for fault detection and some key issues regarding localization of the corresponding defect: • Appropriate techniques, • Switching from electrical testing to fault localization, • Modifying the test pattern to shorten the localization process, • Constructing a localization method based on an IDDQ diagnostic.

The semiconductor industry routinely prepares crosssectional SEM specimens using several traditional techniques. Included in these are cleaving, mechanical polishing, wet chemical etching and focused ion beam (FIB) milling. This presentation deals with a new alternate method for preparation of SEM semiconductor specimens based upon a dedicated broad ion beam instrument. Offered initially as an alternative to wet chemical etching, the instrument was designed to etch and coat SEM and metallographic specimens in one vacuum chamber using inert gas (Ar) ion beams. The system has recently undergone further enhancement by introducing iodine Reactive Ion Beam Etching (RIBE) producing much improved etching/cleaning capabilities compared with inert gas ion beam etching. Further results indicate Ar broad ion beam etching can offer a rapid, simple, more affordable alternative (to FIB machines) for precision cross sections and for “slope cutting,” a technique producing large cross-sections within a short time frame. The overall effectiveness of this system for iodine RIBE etching, for precision cross sectioning and “slope cutting” will be shown for a number of traditional and advanced semiconductor devices.

A new focused-ion-beam (FIB) micro(μ)-sampling technique has recently been developed to facilitate transmission electron microscope (TEM) specimen preparation, while allowing chips or wafer samples to remain intact. A deep trench is FIB-milled to dig out a small, wedge-shaped portion of the sample (or a microwedge) from the samples area of interest, leaving a small, brige-shaped portion (or a microbridge) to support the microwedge. A metal needle is then manipulated into position for lifting the microwedge, i.e., the μ-sample. FIB-assisted deposition (AD) is used to bond the needle to the μ-sample. FIB-milling of the microbridge then separates the μ-sample from the chip or wafer. The separated μ-sample is mounted onto a TEM grid and secured using FIB-AD. The μ-sample is then FIB-thinned further, to a strip of about 0.1 μm thick. All of the above steps are accomplished under vacuum in the FIB system. This design permits a reliable and user-friendly environment for TEM specimen preparation, while keeping chips or wafer samples intact. It also permits operators to repeat TEM inspection and FIB-milling so that precise areas of interest may be made available for TEM inspection. Both cross-sectional and plan view TEM μ-sampling are feasible.

A new analysis method using conventional emission microscopy (EMS) was developed for localizing open defects in CMOS LSIs. EMS is widely used for failure analysis of IDD (power supply current) leakage failures. The root cause of a failure is deduced by considering the emission characteristics associated with the IDD leakage current, emission shape, emission energy spectrum, and exact location on an Si die. Our new technique focuses on the observation of transient photoemission immediately after VDD application. During IDD leakage failure analysis, unique transient photoemission characteristics are observed. Immediately after VDD application, strong photoemission is briefly observed at the drain edge of an n-FET, but disappears after stabilization of the IDD current. We assumed that temporary photoemission would not be generated in transient behavior unless some kind of open defects were located at a specific conductor connected to the gate electrode. This mechanism was verified by nonbiased charge-up contrast of a conventional secondary electron image (SEI) and cross-sectional SEM observation at the defective open location. The dynamic method of observing transient photoemission proposed here is a very effective and practical way for detecting the locations of open failures in CMOS LSIs. Some examples of open mode failure analysis are described, along with cross-sectional TEM observations.

Enhancement of Existing Fault Isolation Techniques for CMOS VLSI Failure Analysis is important in keeping pace with device design and process technologies. Recently, we enhanced our photoemission microscopy capability by applying heat to the device during analysis1. This provided greater defect related light emission from nSRAM test structures and allowed identification of subtle failure modes not observable during room temperature inspection. In the present work, we investigate the theoretical dependencies of emission mechanisms and analyze experimental data to identify the dominant physical mechanisms involved with thermally assisted photoemission. We introduce a thermal factor to help quantify the effect from various light emitting structures. Experimentally, we find that emission mechanisms involving leaky and forward junctions are enhanced by temperature, and propose that the dominant factor for increased signal may be an increasing contribution from phonon absorption rather than phonon emission-based recombination. For emission mechanisms based on impact ionization; however, we find that the emission response is inversely proportional to temperature, and show that mobility degradation is the dominant limiting factor at higher temperatures.