Advanced packaging of electronic components is increasing complexity of single packages containing up to hundreds of individual components in a 3-dimensional arrangement. X-ray nano-tomography enables to resolve these complex structures in 3D with sub-micron resolution for failure analysis. Here we present a study using a cutout from an embedded multi-die interconnect bridge (EMIB) scanned with a custom nano-CT system utilizing a state-of-the-art nano focus X-ray source. For comparison, a scan using a commercial electronics imaging system was performed as well. We demonstrate that micron and sub-micron sized defects can be identified enabling failure analysis on the sub-micron level.

This paper describes the detailed sample preparation of direct Cu-to-Cu bonding in 3D packaging between processor and memory. Different sample preparation techniques are described and compared. The sample preparation methods will then be confirmed by advanced structural characterization and strain measurement. The presence of voids and strain at the bonding interface is associated with the development of device failure.

Advancements in light-induced capacitance alteration (LICA) and optical and ultrasonic beam-induced resistance change ((S)OBIRCH) methods for the localization of open, resistive, and leakage failures in 3D integration technologies are reported. Additionally, a novel sample preparation approach is introduced to improve imaging resolution for optical fault isolation methods. This approach involves re-routing probe pads using a low-profile redistribution layer, realized by conductive inkjet printing, enabling the use of short-working-distance and liquid immersion objectives while probing from the same side of the chip.

The emergence of three-dimensional (3D) semiconductor devices has increased the importance of thermal imaging techniques. This paper presents a dual-capability system combining thermo-reflectance and thermal lock-in imaging (LIT) for high-speed, highly sensitive thermal analysis. We evaluate the hotspot detection capabilities of two-wavelength thermo-reflectance compared to LIT, including results from actual failure analysis cases. Our findings demonstrate the effectiveness of thermo-reflectance detection (TD) imaging for 3D devices where direct optical access to active layers is limited, such as 3D NAND flash memory and BSP-DN structured devices. This approach offers a promising solution for the thermal characterization of complex 3D semiconductor architectures.

The importance of three-dimensional (3D) localization capability is growing as advanced semiconductor devices go to 3D structures. An algorithm for processing lock-in OBIRCH data was developed especially for 3D/4D memory devices. The concept was tested with a simple test sample, which was confirmed to be capable of generating depth separated images.

A commercially available 6T SRAM was examined with an AFM-in-SEM system. A conductive AFM measurement was taken using an AC bias on the backside of the sample with a linear amplifier on the data. Then using a cone-shaped, diamond AFM tip, subsequent scans were made over the field of view at increasingly higher downforce until areas of the chip were worn away. The results provide a survey of implants and structure milling from contact level through the wells of the device. An additional experiment was performed with EBAC.