This paper describes the detailed sample preparation of a solder joint at the level between a semiconductor package and board. Different sample preparation techniques are described and compared. Preparing and targeting a large sample area containing multiple solder bumps is discussed. The sample preparation methods will then be confirmed by advanced structural characterization and strain measurement. The presence of strain is associated with the development of cracks and delamination at the solder joint interface.

Failure analysis on mixed-signal ICs for automotive applications often requires the use of EVBs (evaluation boards) to replicate the failure mode. Typically, automotive ICs are used in conjunction with other components to create automotive modules, such as; PCM (power-train control modules), ECU (engine control units), TCU (transmission control units), etc. EVBs are used to replicate module level functionality, as well as reproduce ATE (automatic test equipment) tests required for analysis. An integral part of EVB design, functionality and performance is related to the IC socket, which is the direct interface between the IC and the EVB. See Figure 1. EVB socket solutions will vary based on the required analysis (backside / topside analysis), package type and IC functionality.

If power modules suffer failures, frequently the destruction energy is so high that the component (and also neighbored circuitry) burns down completely. For failure analysis, just some pieces of carbonized leftovers and molten metal balls are available. Of course, no useful analysis on component level is possible in such cases. However, a combination of system-related failure anamnesis and dedicated measurements on new reference systems and surviving parts of the failed system, allows many useful conclusions towards the failure root cause. This paper highlights the most important approaches and questions to be evaluated in such cases.

Industry and market requirements keep imposing demands in terms of tighter transistor packing, die and component real estate management on the package, faster connections and expanding functionality. This has forced the semiconductor industry to look for novel packaging approaches to allow for 3D stacking of transistors (the so called “More than Moore”). This complex 3D geometry, with an abundance of opaque layers and interconnects, presents a great challenge for failure analysis (FA). Three-dimensional (3D) magnetic field imaging (MFI) has proven to be a natural, useful technique for non-destructively mapping 3D current paths in devices that allows for submicron vertical resolution. 3D X-ray microscopy (XRM) enables 3D tomographic imaging of advanced IC packages without the need to destroy the device. This is because it employs both geometric and optical image magnifications to achieve high spatial resolution. In this paper, we propose a fully nondestructive, 3D-capable workflow for FA comprising 3D MFI and 3D XRM. We present an application of this novel workflow to 3D defect localization in a complex 2.5D device combining high bandwidth memory (HBM) devices and an application specific integrated circuit (ASIC) unit on a Si interposer with a signal pin electrical short failure.

The results presented here show how high-speed simultaneous EBSD and EDS can be used to characterize the essential microstructural parameters in SnPb solder joints with high resolution and precision. Analyses of both intact and failed solder joints have been carried out. Regions of strain localization that are not apparent from the Sn and Pb phase distribution are identified in the intact bond, providing key insights into the mechanism of potential bond failure. In addition, EBSD provides a wealth of quantitative detail such as the relationship between parent Sn grain orientations and Pb coarsening, the morphology and distribution of IMCs on a sub-micron scale and accurate grain size information for all phases within the joint. Such analyses enable a better understanding of the microstructural developments leading up to failure, opening up the possibility of improved accelerated thermal cycling (ATC) testing and better quality control.

In this paper, we demonstrate cases for actual short and open failures in FCB (Flip Chip Bonding) substrates by using novel non-destructive techniques, known as SSM (Scanning Super-conducting Quantum Interference Device Microscopy) and Terahertz TDR (Time Domain Reflectometry) which is able to pinpoint failure locations. In addition, the defect location and accuracy is verified by a NIR (Near Infra-red) imaging system which is also one of the commonly used non-destructive failure analysis tools, and good agreement was made.

This paper is focused on the de-soldering process on VSON package which was mounted on FR4 substrate board after being subjected to environmental stress. Abnormalities were found at package level during Scanning Acoustic Microscopy (SAM) inspection which is considered to be one of the non-destructive failure analysis processes. Root cause finding involved the investigation of the de-soldering equipment which is suspected to be one of the culprits to contribute to the defect during de-soldering process.

In this article, we demonstrate using lock-in thermography (LIT) to perform fault isolation of leakage on a board-mounted device with rough, heterogeneous epoxy encapsulation. It is interesting to observe LIT spot shifting either on the failing unit’s reference pin or the failed pin using a different lock-in frequency. The protection diode of the reference pin is triggered by LIT and the electrical behavior should not be affected by varying lock-in frequencies (0.1 Hz to 25 Hz). The reason for the shifting hot spot is a non-uniform morphology in the epoxy encapsulation, which consists of different thicknesses and voids. This complicated epoxy encapsulation morphology results in a non-uniform heat conduction pathway when a different lock-in frequency is used. In this study, a LIT hot spot will stabilize and remain in a fixed position when the lock-in frequency is increased to greater than 5 Hz and the phase shift is directly proportional to the square-root of the lock-in frequency. This indicates that the heat conduction becomes stable under such a condition, and the phase shift value can still be used for relative depth localization. By overlaying LIT and X-ray imaging, an accurate position of the fault location in the X-Y plane can be detected. A quick and non-destructive 3D fault isolation method for complicated system level failure can be achieved in this way.

Fault localization is a common failure analysis process that is used to detect the anomaly on a faulty device. The Infrared Lock-In Thermography (LIT) is one of the localization techniques which can be used on the packaged chips for identifying the heat source which is a result of active damage. This paper extends the idea that the LIT analysis for fault localization is not only limited to the devices within the silicon die but it also highlights thermal failure indications of other components on the PCB (like capacitors, FETs etc on a system level DC-DC μmodule). The case studies presented demonstrate the effectiveness of using LIT in the Failure analysis process of a system level DC-DC μmodule regulator.

This paper describes the failure analysis methods used to characterize micro cracks that resulted in laser vias of printed circuit boards (PCBs) through case studies of destructive failure analysis. Defects such as cracks in laser vias of PCBs can cause open or low leakage failure mode of module due to improper cleaning during the PCB process, natural oxide films such as brown oxide, or physical forces by use. Therefore, it’s difficult to identify the causes of these phenomena unless proper analytical techniques are used. In this study, multiple analytical techniques are employed to characterize micro cracks in laser vias. The destructive analysis with cross section and ion milling process is used to detect and inspect an accurate micro crack phenomenon of laser via. The characterization analysis using TEM, EDX and SIMS equipment after separating laser vias from a PCB is used to analyze failure cause of micro crack in laser via. This paper will be concluded with a discussion about what physical analysis methods should be used to analyze the causes of micro cracks for laser vias of PCBs.

In this paper, different failure analysis (FA) workflows are showed which combines different FA approaches for fast and efficient fault isolation and root cause analysis in system level products. Two case studies will be presented to show the importance of a well-adjusted failure analysis workflow.

The focus of this paper is to present an interesting case study involving Vishay wire-wound (WSC model) resistor failures, which affected a significant number of production and fielded assemblies. The failures were considered “mission critical”, which was the primary driver necessitating root cause analysis. A disciplined approach to the failure analysis effort was established, which resulted in root cause determination and the generation of appropriate corrective actions. This paper will highlight a non-conventional decapsulation method used to preserve the integrity of the fragile resistive element and a “lucky break” that was instrumental in linking the supplier’s actions to the failures.

The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.

During the search for the root cause of a board level failure, all aspects of the product must be revisited and investigated. These aspects encompass design, materials, and workmanship. In this discussion, the failure investigation involved an S-Band Power Amplifier assembly exhibiting abnormally low RF output power where initial troubleshooting did not provide a clear cause of failure. A detailed fault tree drove investigations that narrowed the focus to a few possible root causes. However, as the investigation progressed, multiple contributors were eventually discovered, some that were not initially considered.

The metal thickness of surface finish is an important consideration when plating on microelectronics. Metal finish thickness should comply with specification requirements to prevent serious reliability concerns. The thickness of metallic coatings is routinely determined by X-ray fluorescence (XRF) spectrometry. For conventional XRF instrumentation, typical focal spot sizes at the sample surface range in diameter from several hundred micrometers up to several millimeters. Micro- XRF focuses or collimates the X-ray beam to significantly smaller spot sizes, ranging from ~30 µm to 2 mm, thus obtaining a representative average of layer properties both at the surface and in-depth layers. This is a critical property for application in semiconductor industry where feature size is becoming progressively smaller. This work describes how a mid-range cost conventional XRF tool can be utilized for small spot size thickness measurement with the addition of a 0.25 mm diameter collimator.

Time Domain Reflectometry (TDR) is an analysis technique for characterizing a transmission environment (PCB traces, cable assemblies, etc.) and identifying the physical location of defects or impedance discontinuities which can quickly narrow the focus of an investigation. This paper introduces the capability and presents several case studies spanning different applications where TDR was useful as a non-destructive analysis technique.

Yellow banding is a phenomenon occurring at an edge(s) in an electronic optical touch screen when the display module emits certain background light. Although it is commonly recognized that the discoloration turns yellowish due to display liquid crystal (LC) cell gap change, the mechanism to create the color change can be different depending on the display designs. This paper discusses an approach to investigate a particular mechanism of forming yellow banding caused by uncured edge fill UV adhesive.

This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.

One issue that faces failure analysis at the system level is impedance mismatched transmission lines resulting from developers pushing the edge of trace layout recommendations. When transmission lines on printed circuit boards are routed in such a way as to allow for impedance mismatches, the effects can be unwanted on the signal that the line carries. Techniques can be used for discovering if capacitance, resistance, or split planes are creating the impedance mismatches that are resulting in the system level failure seen by the customer.

For those attempting fault isolation on computer motherboard power-ground short issues, the optimal technique should utilize existing test equipment available in the debug facility, requiring no specialty equipment as well as needing a minimum of training to use effectively. The test apparatus should be both easy to set up and easy to use. This article describes the signal injection and oscilloscope technique which meets the above requirements. The signal injection and oscilloscope technique is based on the application of Ohm's law in a short-circuit condition. Two experiments were conducted to prove the effectiveness of these techniques. Both experiments simulate a short-circuit condition on the VCC3 power rail of a good working PC motherboard and then apply the signal injection and oscilloscope technique to localize the short. The technique described is a simple, low cost and non-destructive method that helps to find the location of the power-ground short quickly and effectively.