Time Resolved Imaging (TRI) acquisitions allow precise timing analysis of emission spots. Up to date technologies deeply challenge their isolation by hiding the weak ones, under sizing or over sizing visually detectable emission spots and finally by jeopardizing timing resolution. We report on an algorithm based on 1 and 2D signal processing tools which automates the identification of emission sites and optimizes separation between noise and useful signal, even for weak spots surrounding strong emission areas. The application of the algorithm on several sets of data from different types of devices and their results are also discussed.

In this paper, we present a comprehensive overview of several advanced methods and software solutions that we have developed during the years in support of chip diagnostic and characterization in our lab. These techniques apply to the analytical tools in our lab, such as time-integrated and time-resolved emission microscopes, and are devised to help improve productivity and ease of use. In particular we discuss emission-based auto-focusing for detecting very faint signals, processing large sets of images for high-resolution mapping of very large field of views, careful registration of emission images to circuit layout shapes, and advanced processing of the data for extracting the valuable underlying information. In the past, these techniques have been extensively used in support of many diagnostic and characterization applications, and they have been effective enablers for the development of innovative methods and tools.

Analog simulation combined with Time Resolved Light Emission (TRE) can be used to evaluate different fault possibilities and to isolate the most likely fault candidate. In this paper we will describe an improved fault model derived from parasitic layout extraction.

From a designer point of view, the analysis of a failure root cause can quickly become a nightmare if the number of hypothesis provided by a simulation tool is too high. To help solving this kind of problem the use of physical probing measurement can reduce drastically the number of assumptions made by the simulation by invalidating certain hypotheses. The purpose of this paper is to add to the simulation a new source of information based on light emission to solve this kind of problem. Virtual logic diagram computation is able to provide several hypotheses of fault for a given node and data coming from Time Resolved Imaging (TRI) measurement allows extraction of transition pattern for a given node where the assumption has been established. The cross-referencing of this information aims at eliminating wrong hypotheses and making the simulation more reliable.

This paper describes a simulation-based approach to contamination diagnosis. The methodology is based on the contamination-defect fault (CDF) simulator CODEF. CODEF is able to derive circuit-level faults resulting from contamination deposited on an IC cell during fabrication by simulating the manufacturing process flow. The application of CODEF in contamination diagnosis is illustrated with several examples.

This paper describes a fault identification algorithm for combinational and full-scan sequential circuits called FLOSPAT - Fault Localization by Sensitized Path Transformation [1,2]. The goal of fault identification is to localize a fault to the fewest possible gates and to determine the Boolean functions realized by those gates. Instead of choosing a fault model, FLOSPAT uses fault-independent sensitized path tracing [3] to localize functional deviations. Sensitized path transformation is used to adaptively generate test vectors which improve the diagnostic resolution. The output of FLOSPAT is used for physical defect diagnosis by cross-referencing gate-level defect dictionaries generated by the contamination-defect-fault mapper CODEF [4,5,6].

A new logic-model derivation method for leak faults observed by light-emission microscopy (LEM) or in liquid-crystal analysis (LCA) has been developed to verify those faults by comparing them with failures observed on an LSI tester. Since CMOS devices display various kinds of faulty behavior depending on leak resistance, it is essential to include the effects of this resistance in logic models. Considering that the resistance of leaks observed in LEM and LCA ranges from 10 to 10,000 ohm, the new logic models have been derived so that the leak fault could be easily incorporated into logic simulators without SPICE simulation. The feasibility of the proposed method has been demonstrated by using it to diagnose LEM and LCA faults causing logic failure in a 20k-gate logic LSI circuit.

With the ever decreasing trend in accessibility to hardware tools, the need for software tools is becoming greater than ever for IC fault diagnosis. In this paper, we present a process of studying the limitations and capabilities of fault diagnosis using automated Diagnosis tools, such as FastScan™, as applied to a programmable, parallel processing DSP, The Multimedia Video Processor (TMS320C80). Starting with a brief description of the MVP, we describe how FastScan™ is integrated for supporting fault diagnosis. For establishing the effectiveness of FactScan™ as a diagnostic tool, both the simulation and manufacturing modes of evaluation were done. In simulation mode, both the fault model and the heuristics used by the fault diagnosis software are tested by inserting known defects using a focused ion beam (FIB), machine. This process is then repeated with unknown defects in unknown locations. Experiments on several chips demonstrate the value of the tool and its limitations in relation to detection of classic stuck-at faults and some realistic faults, such as bridging defects.

Often in the course of performing root cause failure analysis and fault localization, it can be helpful to have supporting information in the way of a defect model. This is particularly true when physical identification of a defect is unsuccessful. By modeling suspected, theorized, or documented defects in microchip circuitry, the analyst can more clearly show a direct link between defect and circuit failure in support of analysis conclusions.