MOSFET devices are routinely measured at the probe pad level with conventional capacitance-voltage (CV) measurement instruments. Such measurements are done at the front end of line (FEOL) and back end of line (BEOL) process completion levels. The CV data is used to monitor the process and verify certain parametrics such as effective oxide thickness (EOT), Tox, gate drain overlap capacitance (Miller capacitance), trapped charge, diffusion/halo implant oxide leakage, doping concentration, threshold implant level and many others. This type of testing is treated at length in the classic text of Nichollian and Brews [1]. The introduction of Nanoprobe Capacitance Voltage Spectroscopy (NCVS) of discrete MOSFET devices and the method of performing scanning capacitance imaging (SCM) have been previously presented [2]. In that work, the authors used a capacitance sensor to measure the capacitance of an individual failing embedded DRAM capacitor. This paper will describe nanoprobe CV measurements of a discrete finger device from a multiple finger test structure and show comparable results obtained at the probe pad level, using an improved version of the earlier capacitance sensor. By comparing the BEOL test structure measurements with NCVS results from a single finger, we will verify and calibrate the nanoprobing technique.

In case of a node leakage failure in DRAM products, the location of the defect can be spread over the entire deep trench depth of up to six microns, making it very difficult to precisely localize the defects. In addition, the use of surface area enlarging techniques makes it even more difficult to pinpoint the node leakage defect. In this study, first, the node leakage was verified at contact level using the nano-probing technique. In the second step, the sample was deprocessed into the p well level and a current image was obtained, confirming the node leakage to be located below this level. In the third step, the sample was further deprocessed to the edge of the n well level. AFM-based probing provided additional information regarding the location of the node leakage. With these three measurements, the authors confined the node leakage to the small n well region.

Failure Analysis has to deal with challenging questions about stored charges in floating gates in Non Volatile Memories (NVM) when reading does not give expected data. Access to this information will help to understand failure mechanisms. A method to measure on-site programmed charges in Flash EEPROM devices is presented. Scanning Capacitance Microscopy (SCM) is used to directly probe the carrier concentration on Floating Gate Transistor (FGT) channels. The methodology permits mapping channels and active regions from the die backside. Transistor charged values (ON/OFF) are measured and localized with a 15 nm resolution. Both preparation and probing methods are discussed. Applications are demonstrated on two different Flash technologies: a two-transistor cell (2T-cell) from Atmel and a one-transistor cell (1T-cell) from STMicroelectronics.

Implant related issues are hard to detect with conventional techniques for advanced devices manufactured with deep sub-micron technology. This has led to introduction of site-specific analysis techniques. This paper presents the scanning capacitance microscopy (SCM) technique developed from backside of SOI devices for packaged products. The challenge from backside method includes sample preparation methodology to obtain a thin oxide layer of high quality, SCM parameters optimization and data interpretation. Optimization of plasma etching of buried oxide followed by a new method of growing thin oxide using UV/ozone is also presented. This oxidation method overcomes the limitations imposed due to packaged unit not being able to heat to high temperature for growing thermal oxide. Backside SCM successfully profiled both the n and p type dopants in both cache and core transistors.

The usefulness of scattering-type near-field optical microscopy for mapping the material and doping in microelectronic devices at nanoscale resolution is demonstrated. Both amplitude and phase of infrared (λ = 10.7 μm) laser light scattered by a metallised, vibrating AFM tip scanned a few nanometers above the sample are detected and transformed into images showing contrast of materials, as well as of doping concentration. Cross-sections through layers as thin as 20 nm have been clearly imaged.

Root cause for failure of 90 nm body contacted nFETs was identified using scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM). The failure mechanism was identified using both cross sectional imaging and imaging of the active silicon - buried oxide (BOX) interface in plan view. This is the first report of back-side plan view SCM and SSRM data for SOI devices. This unique plan view shows the root cause for the failure is an under doped link up region between the body contacts and the active channel of the device.

By combining transmission electron microscopy (TEM) [1] with scanning capacitance microscopy (SCM) [2], it is possible to enhance our understanding of device failures. At Sandia, these complementary techniques have been utilized for failure analysis in new product development, process validation, and yield enhancement, providing unique information that cannot be obtained with other analytical tools. We have previously used these instruments to identify the root causes of several yield-limiting defects in CMOS device product lines [3]. In this paper, we describe in detail the use of these techniques to identify electrically active silicon dislocations in failed SRAMs and to study the underlying leakage mechanisms associated with these defects.

Scanning Capacitance Microscopy (SCM) has been extensively used for identifying doping issues in semiconductor failure analysis. In this paper, the root causes of two recent problems -- bipolar beta loss and CMOS power leakage -- were verified using SCM images. Another localization method, layer-by-layer circuit repair with IROBIRCH detection, was also utilized to locate possible defects. The resulting failure mechanism for bipolar beta loss is illustrated with a schematic cross section, which shows the leakage path from the emitter to the base. In the case of CMOS power leakage, the abnormal implantation of the Pwell region was identified with the Plane view SCM image.

Accurately measuring parameter mismatch for analog MOSFETs, such as the threshold voltage (Vt) or W/L ratio, is often required in analog circuit failure analysis. The challenge in probing analog MOSFETs using atomic force probing (AFP) is contact resistance. Contact resistance between AFP tips and tungsten contacts can cause large error at high current. This paper discusses measurement error caused by contact resistance and the techniques to identify and reduce the contact resistance effect.

Atomic Force Probe (AFP) techniques are well suited for the electrical characterization of sub-65nm node SOI devices with multiple metal interconnect levels and low-k interlevel dielectric films. This paper discusses the use of these techniques on sub-30nm gatelength SOI MOSFETs.

Traditionally, many semiconductor companies have used SRAM memory to develop their process technologies. The job of the failure analyst is often to physically deprocess the sample and hope to find the defect with only the bit map location to guide them. The success rate has been better in the past when the size of these SRAM cell were bigger. With the technology shrinking every 2 years, the chance of finding physical defects has become less and less. Besides the shrinking SRAM cell geometries, the electrical failure signature for many of the failures is marginal (soft failure), presenting difficult challenges for failure analysis (FA). Physical analysis of these soft SRAM failures at the sub-100nm technologies is often non-visual without detailed isolation and electrical characterization. Therefore, additional techniques are needed to improve the successful FA on newer technologies. In this discussion, we will present the uses of both SCM/SSRM (scanning capacitance microscopy / scanning spreading resistance microscopy) analysis and nanoprobing technique for fail site isolation.

Many of the standard techniques of Failure Analysis (FA) are breaking down or becoming less useful as feature sizes drop below 100nm. The tenth micron milestone appears to be a fundamental limitation to many common techniques. Use of Current Image-Atomic Force Microscopy (CI-AFM) combined with Atomic Force Probing (AFP) brings about a combination of technologies, which allow for extension of FA below the nano-scale.

For years there has been a discrepancy between the importance of complex doping implantation schemes for advanced technology device performance and the ability to accurately measure the carrier concentrations with the gap widening at each technology node. With scanning spreading resistance Microscopy (SSRM) a major step forward in terms of resolution and quantification was achieved especially since the emergence of full diamond tip manufacturability and improvements in sample preparation techniques. This article discusses the non-trivial prerequisites for this success and some examples from the failure analysis routine that show the promising capabilities of SSRM. The examples include technology monitoring and failure analysis in SOI transistors and vertical surrounded gate transistors, as well as failure analysis on yield and performance issues. SSRM has reached a development stage that allows its application as routine tool for 2D-carrier profiling.

Scanning capacitance microscopy (SCM) has become a valuable tool for failure analysis in integrated circuit manufacture. The ability to perform two-dimensional dopant distribution analysis on small, specific structures has been hampered, however, by the imprecision of current polishing techniques. Utilization of focused ion beam (FIB) milling instrumentation to perform precise cross sectioning of specific structures is preferable to manual polishing, although SCM data has not been forthcoming, due in part at least to the thicker amorphous silicon layer. This work examines the thickness of the amorphous silicon layers generated by various sample preparation methods, including conventional polishing, FIB milling, and low-energy FIB milling. In addition, this work provides SCM comparisons of the low energy FIB milling preparation procedure and conventional polishing.

In this study we have investigated the magnetic field associated with a current flowing in a circuit using Magnetic Force Microscopy (MFM). The technique is able to identify the magnetic field associated with a current flow and has potential for failure analysis.

The geometries of several proposed new electronic device structures put constraints on the size of the AFM images that can be obtained in the gate areas. The images that can be obtained on these structures are of a significantly smaller area, at a much higher resolution, than is typically measured. The analysis areas are limited to ~ one-tenth of what is normally scanned. The micro-roughness and feature size information contained in AFM measurements changes with scan size. Care must be taken when introducing such a dramatic change in the measurements being made. Several factors should be considered to determine an appropriate sampling plan and select a proper reference set for these high-resolution measurements. In this paper, several of these factors are discussed in the context of determining a sampling plan and reference targets for sidewall micro-roughness of fins that allow 50 nm analysis areas.

In this paper, scanning thermal conductivity microscopy is used to characterize interconnect defects due to electromigration. Similar features are observed both in the temperature and thermal conductivity micrographs. The key advantage of the thermal conductivity mode is that specimen bias is not required. This is an important advantage for the characterization of defects in large scale integrated circuits. The thermal conductivity micrographs of extrusion, exposed and subsurface voids are presented and compared with the corresponding topography and temperature micrographs.

Traditionally, planar scanning capacitance microscopy has been conducted on samples which have been deprocessed to the level of the substrate and an oxide re-grown over the sample. However, HF used to etch the sample to the substrate can also dissolve shallow junctions. This article documents the ability of scanning capacitance microscopy to be utilized at the level of the contacts leaving the pre-metal dielectric intact. It demonstrates the scalability of this technique across three process generations spanning 0.18 micron, 0.13 micron, and 90 nm nodes. The article documents preliminary data on anomalous contrast observed in contacts at both 0.13 micron node and 90 nm node products. It also demonstrates the ability to distinguish between contacts going to a n-type diffusion, p-type diffusion, and transistor gate. The article also presents a simple model for the CV curves of defective contacts to source/drain diffusions.

The passive voltage contrast (PVC) in this experiment was widely used to detect open/short issues for most failure analyses. However, most of back-end particles were visible, but front-end particles were not. And sometimes only used PVC image, the failure mechanism was un-imaginable. As a result, we needed to collect some electrical data to explain complex PVC image, before physical failure analysis (PFA) was started. This paper shows how to use the scanning probe microscope (SPM) tool to make up PVC method and overcome the physical failure analysis challenge. From our experiment, the C-AFM could provide more information of the defect type and give faster feedback to production lines.

A method to differentiate Gate-to-S/D Gate Oxide Short from non-Gate Oxide Short defect in real products by analyzing the I-V curves acquired by Conducting-Atomic Force Microscopy (C-AFM) is presented. The method allows not only the correct short path to be identified, but also allows differentiation of gate-to-S/D GOS from non-GOS problems, which cannot be reached by passive voltage contrast (PVC) only.