Failure analysis for gate oxide breakdown is increasingly challenging as technology advances to smaller technology nodes. Previously, the cross-sectional passive voltage contrast (XPVC) technique has been successfully utilized in mature technology nodes to isolate gate oxide breakdown locations in complex polysilicon gate structures of planar transistors. However, as semiconductor technology advances, more intricate transistor structures such as FinFET are employed to improve device performance. This paper focuses on the application of the XPVC technique to metal gate structures and examines the challenges associated with its implementation in advanced technology nodes. We demonstrate the applicability of this method in 14nm FinFET devices in simulated gate oxide breakdown experiments showcasing successful sample preparation for subsequent Transmission Electron Microscopy (TEM) analysis.

In the field of semiconductor failure analysis, new sample preparation challenges arise due to the emergence of new chip architectures, such as 3D Back Side Imager (BSI) products. Indeed, these products are constituted of a specific stack: an imager chip at the top associated back-to-back with a digital chip at the bottom on a silicon substrate carrier. All the work presented hereafter is triggered by a nano-probing analysis case on a failing pixel of the imager chip. The analysis consists in characterizing the transistors of the pixel at contact level to isolate the electrical failure. It imposes to keep the integrity of the top chip (imager chip) front-end layers to have the possibility to measure the transistors. It can only be achieved by de-processing from the silicon substrate carrier side. Thus, the particularity of the 3D BSI chip conception implies a more complex delayering protocol than the ones commonly used. In this paper, the sample preparation protocol is presented in detail and its successful implementation is demonstrated through a concrete analysis case in 3D BSI 40 nm technology. This paper also discusses the advantages of the technical solutions implemented to overcome the complexity of the presented architecture.

Cross-sectional analysis plays a crucial role in failure analysis for the identification of root causes associated with implants or junction profiles. Traditionally, this step involves junction staining. Recently, Electron Beam Induced Current (EBIC) analysis has emerged as a valuable alternative, offering the key advantage of visualizing various implantations and junction profiles through non-chemical means. This paper presents an innovative sample preparation technique for cross-sectional EBIC analysis, incorporating an additional step of FIB (Focused Ion Beam) grooving at the target site before cross-sectional polishing. Unlike conventional methods that involve laborious and time-consuming fine cross-sectional polishing, our approach enhances precision and efficiency. With the elimination of the need for extensive polishing, direct access to the target is achieved after rough polishing, thereby expediting the analytical process.

Mechanical sample preparation is a crucial and indispensable step in modern failure analysis (FA). Traditional methods excel in reducing bulk silicon to thicknesses of several tens of micrometers. However, contemporary demands necessitate sample preparation below 10 µm or even below 5 µm, which is challenging, time-consuming, and requires an expensive toolset and advanced operator expertise. Existing methods, which rely on mechanical components for bulk removal, induce mechanical stress and microcracks that can alter the electrical characteristics of the sample. Maintaining the sample's electrical behavior is essential for accurate FA. This paper introduces a novel approach to sample preparation that employs concepts from wafer-level chemical mechanical polishing (CMP). This method ensures reliable sample preparation without introducing microcracks, accurately halts material removal at the shallow trench isolation (STI) – or deep STI - level, and maintains the sample's electrical functionality. The proposed approach is discussed in detail, including successful thinning of various sample types to the STI level, which were subsequently tested for electrical functionality.

In failure analysis, demounting and mounting is one of the steps in preparation for the electrical verification of the device. Performing decapsulation while the unit is mounted on the printed circuit board (PCB) is one of the solutions to limit the repeated demounting, mounting, and re-balling processes. However, it can cause inadvertent damage to the device and the PCB when the acids overflow, which could hinder further electrical verification of the unit. In this study, a new method of decapsulation using aluminum tape is used to protect the device and PCB during the decapsulation process. Results show that the use of aluminum tape is an effective method for decapsulating packaged units on PCB. It can prevent damages such as external lead detachment after demounting, ball pad oxidation, and recovery of device failure due to heat application.

This study presents a revolutionary methodology in an otherwise tedious and inconsistent manual decapsulation process of copper-wired small outline integrated circuit (SOIC) plastic package. The author explains how the consistency was achieved by adopting important changes such as (1) application of the 1-volt electrochemical bias, (2) optimization of etching solution agitation at 3.5 RPM, and (3) adoption of a symmetrical stainless-steel cathode. With the power of consistency, the added benefit of the adoption changes is the correct measurement of wire bond integrity tests such as wire pull, wire diameter, and magnitude of etch. The paper also discusses additional improvements to address the issue of long cycle time via laser ablation.

The ability to precisely remove the internal structures of a semiconductor device, layer-by-layer, is a necessity for semiconductor research and failure analysis investigation. Currently, numerous techniques are used, such as mechanical polishing, chemical etching, and gas assisted plasma focused ion beam (FIB) milling. However, all of these techniques have limitations in that they are unable to: (1) delayer a millimeter-scale area with nanometer-scale uniformity, (2) rapidly remove thick (>300 nm) device layers, or (3) perform automatic and accurate end pointing, which is challenging on thin (≤300 nm) device layers.

In today’s advanced technology world, electronic devices are playing a key role in modern semiconductor products to improve the energy proficiency. These devices are required to be contamination free especially on the bond pad with good adhesion before wire bonding process at the back end. Contamination on the bond pad leads to reliability issues such as pad corrosion, delamination and failure leading to leakage and open fails of electronic devices. Therefore, detection accuracy and sensibility of contamination is important. Auger analysis is the most suitable technique to check bond pad contamination. Auger electron spectroscopy has the capability of analyzing compositional information with excellent spatial resolution. However, charging, noise or artifact is known to be a major concern to the characterization of insulating materials. This paper outlines the strategy that has been utilized to minimize the artifact, noise or charging impact for Auger investigation on a smaller bond pad surrounded by imide passivation layers. The imide passivation layer normally causes the charging effect during Auger analysis, which makes the Auger analysis difficult to be proceed. In addition to that, the charging effect leads to inaccurate analysis. In this paper, we demonstrate a sample preparation method to minimize the charging and artifact of Auger analysis especially for small bond pads.

We describe a fully integrated solution for millimeter-scale delayering of both logic and memory semiconductor devices. The flatness of the delayered device is controlled by an artificial intelligence algorithm, which uses feedback from multiple analytical detectors to control milling parameter adjustments in real time. The result is the precise removal of device layers and a highly planar surface.

This paper presents a development in semiconductor device delayering by broad ion beam milling that offers a uniform delayering area on a millimeter scale. A milling area of this size is made possible by the user's ability to position ion beams individually to cover the desired area. This flexibility in ion beam positioning also enables more precise targeting of an area of interest.

This paper presents a die-level sample preparation technique that uses selective etch chemistry and laser interferometry to expose the entire top metal layer surface for electrical fault isolation. It also describes a novel e-beam based probing technique called StaMPS which is used to isolate logic structure failures through SEM image contrasts. By landing SEM probe tips on exposed metal pads and controlling logic states via an applied bias, different levels of contrast are created highlighting structural failure locations. Die-level sample preparation combined with e-beam fault isolation optimizes turnaround time by delayering die in less than an hour and by locating several types of defects in a single sample.

Integrated circuit (IC) delayering workflows are highly reliant on operator experience to determine processing end points. The current method of end point detection during IC delayering uses qualitative correlations between the thickness and color of dielectric films observed via optical microscopy. The goal of this work is to quantify this relationship using computer vision. As explained in the paper, the authors trained a convolutional neural network to estimate the thickness of dielectric films based on images and measurements recorded during processing. The trained vision model explained 39% of the variance in dielectric film thickness with a mean absolute error of approximately 47 nm. The paper describes the entire workflow, including verification testing, and addresses the primary sources of error.

Global thinning is a technique that enables backside failure analysis and radiation testing. In some devices, it can also lead to increased thresholds for single-event latchup and upset. In this study, we examine the impacts of global thinning on 28 nm node FPGAs. Test devices are thinned to 50, 10, and 3 μm via CNC milling. Lattice damage, in the form of dislocations, extends about 1 μm below the surface, but is removed by polishing with colloidal SiO2. As shown by finite-element modeling, thinning increases compressive global stress in the Si while solder bumps (in flip-chip packages) increase stress locally. The results are confirmed by stress measurements obtained through Raman spectroscopy, although more complex models are needed to account for nonlinear effects in devices thinned to 3 μm and heated to 125°C. Thermal imaging shows that increased local heating occurs with increased thinning, but the maximum temperature difference across the 3-μm die is less than 2°C. Ring oscillators throughout the FPGA fabric slow about 0.5% after thinning and another 0.5% when heated to 125°C, which is attributed to stress changes in the Si.

This paper presents a method that allows top view SEM inspection on GaN devices previously subjected to PEM analysis from the backside and the associated sample preparation procedures. By filling the backside cavity with glob-top resin and epoxying the device to a piece of silicon, it is possible to remove all covering layers with a sequence of wet etches. A dried Ag liquid strap eliminates SEM charging problems and backside laser marks are made visible from the front side using an IR wavelength. The paper describes each step of the process in detail along with the results of the frontside SEM inspection.

This paper discusses advancements that have been made in scanning microwave impedance microscopy (sMIM) and how they are being used to measure various electrical properties in semiconductor devices. It explains that sMIM has a sensitivity of less than 0.1 aF and can measure minute changes in dielectric constant (k-value) and distinguish dopant levels over a wide range of concentrations with a spatial resolution of a few nm. For dielectric films and dopant levels, measurements are conveniently given in log-linear form with a repeatability well within the typical requirements for process monitoring. This, in turn, has enabled reliable quantification, where once only qualitative information was provided. The paper presents real-device results representing a wide range of measurement scenarios.

This work highlights the unique capabilities of time-resolved scanning nonlinear dielectric microscopy as demonstrated in the study of SiO 2 /SiC interfaces. Scanning nonlinear dielectric microscopy (SNDM) is a microwave-based scanning probe technique with high sensitivity to variations in tip-sample capacitance. Time-resolved SNDM, a modified version, is used in this study because it allows simultaneous nanoscale imaging of interface defect density ( D it ) and differential capacitance (d C /d V ), lending itself to correlation analysis and a better understanding of the relationships that influence interface quality. Through cross-correlation analysis, it is shown that D it images are not strongly correlated with simultaneously obtained d C /d V images, but rather with difference images derived from d C /d V images recorded with different voltage sweep directions. The results indicate that the d C /d V images visualize the nonuniformity of the total interface charge density and the difference images reflect that of D it at a particular energy range.

This paper describes optical and electron beam based fault isolation approaches for short and open defects in nanometer-scale through-silicon via (TSV) interconnects. Short defects are localized by photon emission microscopy (PEM) and optical beam-induced current (OBIC) techniques, and open defects are isolated by active voltage contrast imaging in a scanning electron microscope (SEM). The results are confirmed by transmission electron microscopy (TEM) cross-sectioning.

This paper assesses the capabilities of scanning acoustic tomography (SAT) for the analysis of bonded silicon wafers. In order to quantitatively evaluate detectability and resolution, the authors acquired images from samples prepared with artificial voids. The samples consisted of two wafers, a cap wafer and a base wafer with dry-etched pits on a silicon-oxide layer. Cap wafers of different thicknesses were used along with transducers of appropriate focal length. The paper describes the experimental setup and test procedures in detail as well as the results.

The journey to the circuit layer will be described by first discussing baseline processes of laser assisted chemical etching (LACE) steps before the focused ion beam (FIB) workflow. These LACE processes take advantage of a dual 532 nm continuous wave (CW) and pulse laser system, however limitations and overhead that is transferred over to the FIB operator will be demonstrated. Experiments show an additional third 355 nm ultraviolet (UV) pulse laser process introduction into the workflow can further reduce the remaining silicon thickness (RST) relieving FIB overhead. In addition, complex pulse laser patterning techniques will show a refinement to nonuniform produced silicon. Finally, other pulse laser patterning techniques such as polygon etch capability will allow laser etching around and in-between features to enhance circuit layer accessibility for debug operations.

Gate oxide breakdown has always been a critical reliability issue in Complementary Metal-Oxide-Silicon (CMOS) devices. Pinhole analysis is one of the commonly use failure analysis (FA) technique to analysis Gate oxide breakdown issue. However, in order to have a better understanding of the root cause and mechanism, a defect physically without any damaged or chemical attacked is required by the customer and process/module departments. In other words, it is crucial to have Transmission Electron Microscopy (TEM) analysis at the exact Gate oxide breakdown point. This is because TEM analysis provides details of physical evidence and insights to the root cause of the gate oxide failures. It is challenging to locate the site for TEM analysis in cases when poly gate layout is of a complex structure rather than a single line. In this paper, we developed and demonstrated the use of cross-sectional Scanning Electron Microscope (XSEM) passive voltage contrast (PVC) to isolate the defective leaky Polysilicon (PC) Gate and subsequently prepared TEM lamella in a perpendicular direction from the post-XSEM PVC sample. This technique provides an alternative approach to identify defective leaky polysilicon Gate for subsequent TEM analysis.