We describe a fully integrated solution for millimeter-scale delayering of both logic and memory semiconductor devices. The flatness of the delayered device is controlled by an artificial intelligence algorithm, which uses feedback from multiple analytical detectors to control milling parameter adjustments in real time. The result is the precise removal of device layers and a highly planar surface.

In today’s advanced technology world, electronic devices are playing a key role in modern semiconductor products to improve the energy proficiency. These devices are required to be contamination free especially on the bond pad with good adhesion before wire bonding process at the back end. Contamination on the bond pad leads to reliability issues such as pad corrosion, delamination and failure leading to leakage and open fails of electronic devices. Therefore, detection accuracy and sensibility of contamination is important. Auger analysis is the most suitable technique to check bond pad contamination. Auger electron spectroscopy has the capability of analyzing compositional information with excellent spatial resolution. However, charging, noise or artifact is known to be a major concern to the characterization of insulating materials. This paper outlines the strategy that has been utilized to minimize the artifact, noise or charging impact for Auger investigation on a smaller bond pad surrounded by imide passivation layers. The imide passivation layer normally causes the charging effect during Auger analysis, which makes the Auger analysis difficult to be proceed. In addition to that, the charging effect leads to inaccurate analysis. In this paper, we demonstrate a sample preparation method to minimize the charging and artifact of Auger analysis especially for small bond pads.

This paper presents a development in semiconductor device delayering by broad ion beam milling that offers a uniform delayering area on a millimeter scale. A milling area of this size is made possible by the user's ability to position ion beams individually to cover the desired area. This flexibility in ion beam positioning also enables more precise targeting of an area of interest.

This paper presents a die-level sample preparation technique that uses selective etch chemistry and laser interferometry to expose the entire top metal layer surface for electrical fault isolation. It also describes a novel e-beam based probing technique called StaMPS which is used to isolate logic structure failures through SEM image contrasts. By landing SEM probe tips on exposed metal pads and controlling logic states via an applied bias, different levels of contrast are created highlighting structural failure locations. Die-level sample preparation combined with e-beam fault isolation optimizes turnaround time by delayering die in less than an hour and by locating several types of defects in a single sample.

Integrated circuit (IC) delayering workflows are highly reliant on operator experience to determine processing end points. The current method of end point detection during IC delayering uses qualitative correlations between the thickness and color of dielectric films observed via optical microscopy. The goal of this work is to quantify this relationship using computer vision. As explained in the paper, the authors trained a convolutional neural network to estimate the thickness of dielectric films based on images and measurements recorded during processing. The trained vision model explained 39% of the variance in dielectric film thickness with a mean absolute error of approximately 47 nm. The paper describes the entire workflow, including verification testing, and addresses the primary sources of error.

Global thinning is a technique that enables backside failure analysis and radiation testing. In some devices, it can also lead to increased thresholds for single-event latchup and upset. In this study, we examine the impacts of global thinning on 28 nm node FPGAs. Test devices are thinned to 50, 10, and 3 μm via CNC milling. Lattice damage, in the form of dislocations, extends about 1 μm below the surface, but is removed by polishing with colloidal SiO2. As shown by finite-element modeling, thinning increases compressive global stress in the Si while solder bumps (in flip-chip packages) increase stress locally. The results are confirmed by stress measurements obtained through Raman spectroscopy, although more complex models are needed to account for nonlinear effects in devices thinned to 3 μm and heated to 125°C. Thermal imaging shows that increased local heating occurs with increased thinning, but the maximum temperature difference across the 3-μm die is less than 2°C. Ring oscillators throughout the FPGA fabric slow about 0.5% after thinning and another 0.5% when heated to 125°C, which is attributed to stress changes in the Si.

This paper presents a method that allows top view SEM inspection on GaN devices previously subjected to PEM analysis from the backside and the associated sample preparation procedures. By filling the backside cavity with glob-top resin and epoxying the device to a piece of silicon, it is possible to remove all covering layers with a sequence of wet etches. A dried Ag liquid strap eliminates SEM charging problems and backside laser marks are made visible from the front side using an IR wavelength. The paper describes each step of the process in detail along with the results of the frontside SEM inspection.

This paper discusses advancements that have been made in scanning microwave impedance microscopy (sMIM) and how they are being used to measure various electrical properties in semiconductor devices. It explains that sMIM has a sensitivity of less than 0.1 aF and can measure minute changes in dielectric constant (k-value) and distinguish dopant levels over a wide range of concentrations with a spatial resolution of a few nm. For dielectric films and dopant levels, measurements are conveniently given in log-linear form with a repeatability well within the typical requirements for process monitoring. This, in turn, has enabled reliable quantification, where once only qualitative information was provided. The paper presents real-device results representing a wide range of measurement scenarios.

This work highlights the unique capabilities of time-resolved scanning nonlinear dielectric microscopy as demonstrated in the study of SiO 2 /SiC interfaces. Scanning nonlinear dielectric microscopy (SNDM) is a microwave-based scanning probe technique with high sensitivity to variations in tip-sample capacitance. Time-resolved SNDM, a modified version, is used in this study because it allows simultaneous nanoscale imaging of interface defect density ( D it ) and differential capacitance (d C /d V ), lending itself to correlation analysis and a better understanding of the relationships that influence interface quality. Through cross-correlation analysis, it is shown that D it images are not strongly correlated with simultaneously obtained d C /d V images, but rather with difference images derived from d C /d V images recorded with different voltage sweep directions. The results indicate that the d C /d V images visualize the nonuniformity of the total interface charge density and the difference images reflect that of D it at a particular energy range.

This paper describes optical and electron beam based fault isolation approaches for short and open defects in nanometer-scale through-silicon via (TSV) interconnects. Short defects are localized by photon emission microscopy (PEM) and optical beam-induced current (OBIC) techniques, and open defects are isolated by active voltage contrast imaging in a scanning electron microscope (SEM). The results are confirmed by transmission electron microscopy (TEM) cross-sectioning.

This paper assesses the capabilities of scanning acoustic tomography (SAT) for the analysis of bonded silicon wafers. In order to quantitatively evaluate detectability and resolution, the authors acquired images from samples prepared with artificial voids. The samples consisted of two wafers, a cap wafer and a base wafer with dry-etched pits on a silicon-oxide layer. Cap wafers of different thicknesses were used along with transducers of appropriate focal length. The paper describes the experimental setup and test procedures in detail as well as the results.

The journey to the circuit layer will be described by first discussing baseline processes of laser assisted chemical etching (LACE) steps before the focused ion beam (FIB) workflow. These LACE processes take advantage of a dual 532 nm continuous wave (CW) and pulse laser system, however limitations and overhead that is transferred over to the FIB operator will be demonstrated. Experiments show an additional third 355 nm ultraviolet (UV) pulse laser process introduction into the workflow can further reduce the remaining silicon thickness (RST) relieving FIB overhead. In addition, complex pulse laser patterning techniques will show a refinement to nonuniform produced silicon. Finally, other pulse laser patterning techniques such as polygon etch capability will allow laser etching around and in-between features to enhance circuit layer accessibility for debug operations.

Gate oxide breakdown has always been a critical reliability issue in Complementary Metal-Oxide-Silicon (CMOS) devices. Pinhole analysis is one of the commonly use failure analysis (FA) technique to analysis Gate oxide breakdown issue. However, in order to have a better understanding of the root cause and mechanism, a defect physically without any damaged or chemical attacked is required by the customer and process/module departments. In other words, it is crucial to have Transmission Electron Microscopy (TEM) analysis at the exact Gate oxide breakdown point. This is because TEM analysis provides details of physical evidence and insights to the root cause of the gate oxide failures. It is challenging to locate the site for TEM analysis in cases when poly gate layout is of a complex structure rather than a single line. In this paper, we developed and demonstrated the use of cross-sectional Scanning Electron Microscope (XSEM) passive voltage contrast (PVC) to isolate the defective leaky Polysilicon (PC) Gate and subsequently prepared TEM lamella in a perpendicular direction from the post-XSEM PVC sample. This technique provides an alternative approach to identify defective leaky polysilicon Gate for subsequent TEM analysis.

Physical FA innovations in advanced flip-chip devices are essential, especially for die-level defects. Given the increasing number of metal layers, traditional front-side deprocessing requires a lot of work on parallel lapping and wet etching before reaching the transistor level. Therefore, backside deprocessing is often preferred for checking transistor-level defects, such as subtle ESD damage. This paper presents an efficient technique that involves precise, automated die thinning (from 760µm to 5µm), high-resolution fault localization using a solid immersion lens, and rigorous KOH etch. Using this technique, transistor-level damage was revealed on advanced 7nm FinFET devices with flip-chip packaging.

Three-dimensional device (FinFET) doping requirements are challenging due to fin sidewall doping, crystallinity control, junction profile control, and leakage control in the fin. In addition, physical failure analyses of FinFETs can frequently reach a “dead end” with a No Defect Found (NDF) result when channel doping issues are the suspected culprit (e.g., high Vt, low Vt, low gain, sub-threshold leakage, etc.). In new technology development, the lack of empirical dopant profile data to support device and process models and engineering has had, and continues to have, a profound negative impact on these emerging technologies. Therefore, there exists a critical need for dopant profiling in the industry to support the latest technologies that use FinFETs as their fundamental building block [1]. Here, we discuss a novel sample preparation method for cross-sectional dopant profiling of FinFET devices. Our results show that the combination of low voltage (<500eV), shallow angle (~10 degree) ion milling, dry etching, and mechanical polishing provides an adequately smooth surface (Rq<5Å) and minimizes surface amorphization, thereby allowing a strong Scanning Capacitance Microscopy (SCM) signal representative of local active dopant (carrier) concentration. The strength of the dopant signal was found to be dependent upon mill rate, electrical contact quality, amorphous layer presence and SCM probe quality. This paper focuses on a procedure to overcome critical issues during sample preparation for dopant profiling in FinFETs.