Abstract The journey to the circuit layer will be described by first discussing baseline processes of laser assisted chemical etching (LACE) steps before the focused ion beam (FIB) workflow. These LACE processes take advantage of a dual 532 nm continuous wave (CW) and pulse laser system, however limitations and overhead that is transferred over to the FIB operator will be demonstrated. Experiments show an additional third 355 nm ultraviolet (UV) pulse laser process introduction into the workflow can further reduce the remaining silicon thickness (RST) relieving FIB overhead. In addition, complex pulse laser patterning techniques will show a refinement to nonuniform produced silicon. Finally, other pulse laser patterning techniques such as polygon etch capability will allow laser etching around and in-between features to enhance circuit layer accessibility for debug operations.

Abstract Gate oxide breakdown has always been a critical reliability issue in Complementary Metal-Oxide-Silicon (CMOS) devices. Pinhole analysis is one of the commonly use failure analysis (FA) technique to analysis Gate oxide breakdown issue. However, in order to have a better understanding of the root cause and mechanism, a defect physically without any damaged or chemical attacked is required by the customer and process/module departments. In other words, it is crucial to have Transmission Electron Microscopy (TEM) analysis at the exact Gate oxide breakdown point. This is because TEM analysis provides details of physical evidence and insights to the root cause of the gate oxide failures. It is challenging to locate the site for TEM analysis in cases when poly gate layout is of a complex structure rather than a single line. In this paper, we developed and demonstrated the use of cross-sectional Scanning Electron Microscope (XSEM) passive voltage contrast (PVC) to isolate the defective leaky Polysilicon (PC) Gate and subsequently prepared TEM lamella in a perpendicular direction from the post-XSEM PVC sample. This technique provides an alternative approach to identify defective leaky polysilicon Gate for subsequent TEM analysis.

Abstract Physical FA innovations in advanced flip-chip devices are essential, especially for die-level defects. Given the increasing number of metal layers, traditional front-side deprocessing requires a lot of work on parallel lapping and wet etching before reaching the transistor level. Therefore, backside deprocessing is often preferred for checking transistor-level defects, such as subtle ESD damage. This paper presents an efficient technique that involves precise, automated die thinning (from 760µm to 5µm), high-resolution fault localization using a solid immersion lens, and rigorous KOH etch. Using this technique, transistor-level damage was revealed on advanced 7nm FinFET devices with flip-chip packaging.

Abstract Three-dimensional device (FinFET) doping requirements are challenging due to fin sidewall doping, crystallinity control, junction profile control, and leakage control in the fin. In addition, physical failure analyses of FinFETs can frequently reach a “dead end” with a No Defect Found (NDF) result when channel doping issues are the suspected culprit (e.g., high Vt, low Vt, low gain, sub-threshold leakage, etc.). In new technology development, the lack of empirical dopant profile data to support device and process models and engineering has had, and continues to have, a profound negative impact on these emerging technologies. Therefore, there exists a critical need for dopant profiling in the industry to support the latest technologies that use FinFETs as their fundamental building block [1]. Here, we discuss a novel sample preparation method for cross-sectional dopant profiling of FinFET devices. Our results show that the combination of low voltage (<500eV), shallow angle (~10 degree) ion milling, dry etching, and mechanical polishing provides an adequately smooth surface (Rq<5Å) and minimizes surface amorphization, thereby allowing a strong Scanning Capacitance Microscopy (SCM) signal representative of local active dopant (carrier) concentration. The strength of the dopant signal was found to be dependent upon mill rate, electrical contact quality, amorphous layer presence and SCM probe quality. This paper focuses on a procedure to overcome critical issues during sample preparation for dopant profiling in FinFETs.