Decapsulation of silver wire bonded packages with known techniques often results in damaged silver wires. The chemical properties of silver and silver compounds make silver bond wire inherently susceptible to etching damage by acid, conventional plasma, and oxygen-based Microwave Induced Plasma (MIP). In this paper we solve this problem by developing a specific decapsulation chemistry, based on a hydrogen-containing MIP, for artifact-free decapsulation of silver wire bonded packages.

Backside silicon removal provides an avenue for a number of modern non-destructive and circuit edit techniques. Visible light microscopy, electron beam microscopy, and focused ion beam circuit edit benefit from a removal of back side silicon from the integrated circuit being examined. Backside milling provides a potential path for rapid sample preparation when thinned or ultrathinned samples are required. However, backside milling is an inherently destructive process and can damage the device function, rendering it no longer useful for further nondestructive analysis. Recent methods of backside milling do not guarantee device functionality at a detected end point without a priori knowledge. This work presents a methodology for functional end point detection during backside milling of integrated circuit packaging. This is achieved by monitoring second order effects in response to applied device strain, which guide the milling procedure, avoiding destructive force as the backside material is removed. Experimental data suggest a correlation between device power consumption waveforms and second order effects which inform an in situ functional end point. Keywords: functional end point, side-channel analysis, backside thinning, milling, machine learning, second order effects

Infrared optical probing techniques that have significant applications to and continued development for silicon physical debug have existed for decades. More recently, resolution enhancement achieved by improving numerical aperture, etc. have reached fundamental limits and the ability for resolution to match node scaling with radiation transparent to silicon (photon energy < silicon bandgap) becomes diffraction limited for some 10nm and many future process nodes. Decreasing the wavelength used for imaging and signal acquisition can improve resolution; however, it is well documented that absorption increases sharply for photons with energy greater than the bandgap of the bulk substrate material. Significant reduction in the thickness of the backside substrate material can be performed to achieve acceptable transmission through the absorbing substrate, but the requirement for very thin sample preparation significantly modifies the thermal system surrounding active circuitry. Here, high aspect ratio trenches are shown to offer a unique method to take advantage of thick silicon (> 100µm) for lateral heat dissipation as well as thin silicon (< 2µm) for minimally absorbing optical path in close proximity to enable case-by-case preparation methods for postsilicon labs faced with visible light resolution requirements on high power density circuits.

This paper introduces a novel sample preparation method using plasma focused ion-beam (pFIB) milling at low grazing angle. Efficient and high precision preparation of site-specific cross-sectional samples with minimal alternation of device parameters can be achieved with this method. It offers the capability of acquiring a range of electrical characteristic signals from specific sites on the cross-section of devices, including imaging of junctions, Fins in the FinFETs and electrical probing of interconnect metal traces.

The size of devices on state-of-the-art integrated circuits continues to decrease with each technology node, which drives the need to continually improve the resolution of electrical failure analysis techniques. Solid immersion lenses are commonly used in combination with infrared light to perform analysis from the backside of the device, but typically only have resolutions down to ~200 nm. Improving resolution beyond this requires the use of shorter wavelengths, which in turn requires a silicon thickness in the 2 to 5 µm range. Current ultra-thinning techniques allow consistent thinning to ~10 µm. Thinning beyond this, however, has proven challenging. In this work, we show how broad beam Ar ion milling can be used to locally thin a device’s backside silicon until the remaining silicon thickness is < 5 µm.

Demarest et al. concluded in their previous report that a ten times improvement in placement accuracy was required to enable automated transmission electron microscopy (TEM) sample preparation, and wafer alignment by GDS coordinates demonstrated a factor of two improvement in comparison to optical or scanning electron microscope based processes. This paper provides an additional update on this project. The study is about a GDS based process developed to simplify the complicated workflow for examining discrete electrical failures. The results of this study indicated that the recipe prototype developed on a test structure had a unique feature that consisted of an approximately 45nm by 200nm Cu line segment. Executing the prototype recipe on a wafer at the same process point fabricated 6 months after the original wafer yielded four identical successful samples of about 30nm sample thickness. This technique can thus be extended to large 2D arrays of small structures.

In this paper, we present methods for targeted silicon thinning by contour milling to overcome challenges associated with thinning large devices to under 5 µm remaining silicon thickness. Implementation of these techniques are expected to improve the yield of ultra-thin sample preparation and thermal stability of the device through electrical failure analysis for subsequent physical failure analysis. Using a computer numerical controlled milling system, the natural device bow is exploited to thin a specified area of interest by stage tilting before 2D milling. To target a larger area of interests, contour maps are rigged to thin an area preferentially while remaining compatible with existing workflows. Electrical testing have found improved thermal stability of the locally thinned samples over globally thinned samples.

Driven by the cost reduction and miniaturization, Wafer Level Chip Scale Packaging (WLCSP) has experienced significant growth mainly driven by mobile consumer products. Depending on the customers or manufacturing needs, the bare silicon backside of the WLCSP may be covered with a backside laminate layer. In the failure analysis lab, in order to perform the die level backside fault isolation technique using Photon Emission Microscope (PEM) or Laser Signal Injection Microscope (LSIM), the backside laminate layer needs to be removed. Most of the time, this is done using the mechanical polishing method. This paper outlines the backside laminate removal method of WLCSP using a near infrared (NIR) laser that produces laser energy in the 1,064 nm range. This method significantly reduces the sample preparation time and also reduces the risk of mechanical damage as there is no application of mechanical force. This is an effective method for WLCSP mounted on a PCB board.

In the back-end assembly process, all of the packages will be tested prior to disposition to the customers in order to filter out any device with failure. For a reject unit with an unknown failure mechanism, it will be subjected to a comprehensive failure analysis (FA) to identify the root cause of the failure. Non-destructive verification, following by front-side decapsulation and internal physical inspection is the common way to visualise and identify the physical defect that usually causes the failure of a device during the back-end assembly process. For certain failures, visualization of the defect might not be straight forward after the decapsulation because the defect may be embedded or buried underneath a layer or wedge bond on the die. In this case, a more complicated FA analysis flow which comprises various precision techniques such as parallel lapping, hotspot localisation and focused-ion-beam (FIB) analyses will be needed to thin down the top layer/wedge bond for a precise localisation of the defect prior to precision analysis by FIB. However, the process to thin down the top layer/wedge bond with an exposed die of a partially decapsulated package is a tricky job as artefacts such as crack/scratches on die are likely to be introduced during the process of polishing. Also it is relatively difficult to control the thickness and levelling of the top layer/wedge bond during the thinning process. In this work, we developed a method that allows the analyst to re-cap the partially decapped package, and also to precisely measure and thin down the top layer to an accuracy of less than < 2um without the introduction of artefacts.

Gallium Arsenide (GaAs) integrated circuits have become popular these days with superior speed/power products that permit the development of systems that otherwise would have made it impossible or impractical to construct using silicon semiconductors. However, failure analysis remains to be very challenging as GaAs material is easily dissolved when it is reacted with fuming nitric acid used during standard decapsulation process. By utilizing enhanced chemical decapsulation technique with mixture of fuming nitric acid and concentrated sulfuric acid at a low temperature backed with statistical analysis, successful plastic package decapsulation happens to be reproducible mainly for die level failure analysis purposes. The paper aims to develop a chemical decapsulation process with optimum parameters needed to successfully decapsulate plastic molded GaAs integrated circuits for die level failure analysis.

Today, copper pillar bumping now in high volume production for mobile electronics is also a transformative technology for next generation flip chip [1] interconnects which offers advantages in many designs while meeting current and future requirements. With the continuous shrinking dimensions of semiconductor devices, the package’s design and size are approaching the dimensions of the singulated die. Moreover, failure analysis involving copper pillar packages would be the major challenges faced by analysts as copper pillar devices in nature hides its solder joints beneath its die causing obstruction in quality inspection as well as judging its solder joint strength. Chemical wet etch or deprocessing [2] by using potassium hydroxide (KOH) to remove all silicon die have disadvantages of over etching on silicon substrate and tin (Sn) surrounding the Cu pillar. Therefore, quality of sample preparation is critical and new methodology is needed.

Accurate root cause determination of integrated circuit devices necessitates the preservation of evidence during failure analysis. Identifying the cause of systemic defects requires capturing physical evidence provided by very few customer returns. Each piece of physical evidence is valuable due to the scarcity of returns in most cases less than 1 ppm. Harvesting infrequent physical evidence requires that each attempt to decapsulate a fail unit has a high probability of retaining the material that caused the defect. A measured method that retains the critical evidence is the fastest way to solve a defect driven systemic failure mechanism because one gathers the evidence more efficiently. This paper presents two case studies of improved evidence gathering using halogen-free microwave induced plasma (MIP) decapsulation during the root cause investigations. This relatively new method of decapsulation enabled us to preserve evidence, including any changes to the metal and die surface structures along with the presence of contaminants or by-products of failure mechanisms.

With the introduction of CNC-based milling systems, it became possible to more uniformly deconstruct silicon devices for through-silicon electrical fault isolation techniques that feature either a convex or concave geometry or by thermally relaxing the device. This paper presents a novel methodology for uniform mechanical deprocessing of stacked memory modules using a CNC milling system. The PCB (FR4) substrate has been identified as the primary mechanism influencing both the profile of the device and relaxation that occurs during device deconstruction. Examples showing this effect are provided on both pre- and post-processed devices where a difference in symmetry can be observed. Utilizing this new strategy, it is possible to restore a more symmetrical profile that is easier to process with a CNC milling machine.

Focused ion beam (FIB) techniques are often used when delayering semiconductor devices. However, using FIB technology for device delayering has limitations. One of these limitations prevents the exposure of a large slope area on the sample, which reveals all layers simultaneously. The delayering process is complex and requires prior process knowledge, such as cross-section architecture, composition, and layer uniformity. This paper discusses advances in semiconductor device deprocessing for product development, failure analysis, and quality control using low-energy, argon broad ion beam (BIB) milling. Ar BIB milling is a practical solution for accurate delayering of advanced microelectronic devices. Results of the spot milling of a whole 300 mm wafer experiment and top-down delayering of wafer pieces experiment show that successful device delayering can be achieved by either spot milling or layer-by-layer milling. These two strategies are easily achieved, for either small wafer pieces or full 300 mm wafer investigation.

Chemical etching is commonly used in exposing the die surface from die front-side and die backside because of its quick etching time, burr-free and stress-free. However, this technique is risky when performing copper lead frame etching during backside preparation on small and non-exposed die paddle package. The drawback of this technique is that the copper leads will be over etched by 65% Acid Nitric Fuming even though the device’s leads are protected by chemical resistance tape. Consequently, the device is not able to proceed to any other further electrical measurements. Therefore, we introduced mechanical preparation as an alternative solution to replace the existing procedure. With the new method, we are able to ensure the copper leads are intact for the electrical measurements to improve the effectiveness and accuracy of physical failure analysis.

An in situ air gaps fill-in approach was investigated by conducting a convenient way in dual-beam FIB. We employed a well-controlled deposition to precisely fill carbon into air gaps. It greatly reduced formation of the artifacts and avoided the profiles of air gaps by reducing striations and damages during FIB milling. Generally, the effect of air gaps between wordlines or between metal lines, as well as some unexpected defect voids can be eliminated in most cases if this ideal method is applied.

The semiconductor industry is constantly investigating new methods that can improve both the quality of TEM lamella and the speed at which they can be created. To improve throughput, a combination of FIB-based preparation and ex situ lift-out (EXLO) techniques have been used. Unfortunately, the carbon support on the EXLO grid presents problems if the lamella needs to be thinned once it is on the grid. In this paper, we present low-energy (<1 keV), narrow-beam (<1 μm diameter), Ar+ ion milling as a method of preparing electron-transparent and gallium-free EXLO FIB specimens.

Device failure analysis typically requires multiple systems for fault identification, preparation and analysis. In this paper we discuss the practicalities and limits of using a single FIBSEM system for a complete failure analysis workflow. The theoretical requirements of using a nanomanipulator for both lamella lift out and electrical testing are discussed and the current capabilities of windowless X-rays detectors for chemical analysis demonstrated. When the required resolution for failure analysis exceed the limits of a FIBSEM and TEM is required, the combination of the nanomanipulator and X-ray detector for advanced lift out and thickness controlled thinning techniques are demonstrated to prepare exceptional quality lamellae.

An advanced sample preparation protocol using Xe+ Plasma FIB for increasing FA throughput is proposed. We prepared cross-sections of 400 μm and wider in challenging samples such as a BGA (CSP), bond wires in mold compound or a TSV array. These often suffer from FIB milling artifacts. The unsatisfactory quality of the cross-section face is mainly due to extremely different milling rates of the various materials (polyimide, tin, copper, mold compound, platinum), ion beam induced ripples [1] or due to significant surface topography. We explored the usability of the protocol for standard cross-sections and also tested the preparation of TEM lamellae. The process parameters of the proposed approach were compared with the standard methods of Xe+ Plasma FIB FA with respect to preparation time and cross-section quality. Aiming for ultimate results, we incorporated the Rocking stage technique which also greatly improves cross-section quality.

Ex situ lift out is fast, easy, and reproducible, and adds flexibility for either frontside or backside manipulation of focused ion beam milled specimens. ex situ lift out methods may be enhanced by eliminating electrostatic forces. In addition, optimizing the geometry of the specimen relative to the probe improves the Van der Waals forces responsible for the lift out and subsequent manipulation of focused ion beam prepared specimens.