Physical characterization of individual process steps and their interaction with other processes is a key element during development as well as manufacturing of semiconductor technology. This paper presents a number of examples that illustrate the usefulness of the combination of sample wet-chemical staining techniques with the latest generation SEM imaging capabilities. The examples show how sample preparation and imaging conditions have to be tailored to the specific needs. The combination of application-tailored chemical decoration with high-resolution material contrast SEM imaging has proven to be a powerful technique for the characterization of manufacturing process steps. Only with the novel imaging modes available in the latest generation SEM instruments, it became possible to perform investigations with fast turnaround times and on large sample areas.

Failure analysis of automotive semiconductor devices requires highly reliable techniques to guaranty the success of artifact-free decapsulation with high repeatability and reproducibility. With the introduction of new qualification standards, new mold compounds, and new packaging structures, advanced decapsulation tools are needed to enable failure analysis to achieve a high success rate. Microwave Induced Plasma (MIP) machine has been developed as an advanced decapsulation solution. The CF4-free MIP etching ensures artifact-free exposure of bond wires made of new materials, the die, passivation, bond pads, and original failure sites. The high mold compound etching rate, high etching selectivity of mold compound to wire/pad/passivation/die, and the fully automatic process are the unique features of MIP decapsulation. Comparisons are made between acid, conventional plasma with CF4, and CF4-free MIP decapsulation. Multiple case studies are discussed that address challenging automotive semiconductor device decapsulation, including bare copper wire, copper redistribution layer, exposed power copper metal, stitch bond on silver plated leadframe, complex mold compound, Bond-Over-Active-Circuit, eWLB, and localized decapsulation.

Visible Light (or Laser) Probing (VLP) is an exciting new development in Laser Voltage Probing (LVP) technology because it promises a dramatic improvement in resolution over current Near Infrared (NIR) solutions [1-3]. To have adequate visible light transmission for waveform probing and modulation mapping, however, ultrathinning of the silicon backside to <2-5 μm is required. The use of solid immersion lens (SIL) technology places additional requirements on sample preparation. In this paper, we present a simple, SIL compatible technique for VLP sample preparation.

Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. When the remaining silicon is reduced, some redistribution of stress is expected, possibly altering the performance (timing) of integrated circuits in addition to electron-hole pair generation. In this work, a study of the electrical invasiveness due to grinding and polishing silicon integrated circuits to ultra-thin (< 5 um global, ~ 1 um local) remaining thickness is presented.

High-power modules incorporating insulated gate bipolar transistors (IGBT) include a thick layer of dielectric insulating gel to prevent arcing. Chemical methods currently used to remove the gel are slow, taking up to 24 hours, while generating as much as a half-gallon of waste. High-pressure wet jets have also been used, but they cause significant damage to wire bonds. In this paper, we present a fast and efficient process for removing insulating gel from high-power modules. The method uses a CO2 laser to selectively open windows in the gel that are then filled with a few drops of solvent followed by a DI water rinse. The entire process takes less than an hour to prepare samples for inspection and analysis, while generating just 200ml of waste.

Copper pillar WLCSP device embedded in large PCB module with passive devices to create one hybrid package are growing widely in smart communication and mobile electronic devices. The crucial challenges in electrical testing and failure analysis on it are to remove the embedded copper pillar CSP device from the module without inducing mechanical defects, and solder ball placement on the CSP for ATE testing. This paper discusses the sample preparation process step-by-step, which includes de-soldering of external components from the PCB, top side up and down parallel polishing to remove copper pillars, chemical etching the PCB module, solder ball placement on CSP devices and the soldering process on a plain coupon board. The established process enables electrical testing, evaluations and failure analysis performed on a demounted CSP device. A simulation of an electrical testing and failure analysis will also be highlighted in this paper.

Novel techniques to expose substrate-level defects are presented in this paper. New techniques such as inter-layer dielectric (ILD) thinning, high keV imaging, and XeF2 poly etch overflow are introduced. We describe these techniques as applied to two different defects types at FEOL. In the first case, by using ILD thinning and high keV imaging, coupled with focused ion beam (FIB) cross section and scanning transmission electron microscopy (STEM,) we were able to judge where to sample for TEM from a top down perspective while simultaneously providing the top down images giving both perspectives on the same sample. In the second case we show retention of the poly Si short after removal of CoSi2 formation on poly. Removal of the CoSi2 exposes the poly Si such that we can utilize XeF2 to remove poly without damaging gate oxide to reveal pinhole defects in the gate oxide. Overall, using these techniques have led to 1) increased chances of successfully finding the defects, 2) better characterization of the defects by having a planar view perspective and 3) reduced time in localizing defects compared to performing cross section alone.

In wafer fabrication, a silicon nitride (Si3N4) layer is widely used as passivation layer. To qualify the passivation layers, traditionally chemical recipe PAE (H3PO4+ HNO3) is used to conduct passivation pinhole test. However, it is very challenging for us to identify any pinholes in the Si3N4 layer with different layers underneath. For example, in this study, the wafer surface is Si3N4 layer and the underneath layer is silicon substrate. The traditional receipt of PAE cannot be used for passivation qualification. In this paper, we will report a new recipe using KOH solution to identify the pinhole in the Si3N4 passivation layer.

This paper discussed on how the importance of failure analysis to identify the root cause and mechanism that resulted in the MEMS failure. The defect seen was either directly on the MEMS caps or the CMOS integrated chip in wafer fabrication. Two case studies were highlighted in the discussion to demonstrate how the FA procedures that the analysts had adopted in order to narrow down to the defect site successfully on MEMS cap as well as on CMOS chip on MEMS package units. Besides the use of electrical fault isolation tool/technique such as TIVA for defect localization, a new physical deprocessing approach based on the cutting method was performed on the MEMS package unit in order to separate the MEMS from the Si Cap. This approach would definitely help to prevent the introduction of particles and artifacts during the PFA that could mislead the FA analyst into wrong data interpretation. Other FA tool such as SEM inspection to observe the physical defect and Auger analysis to identify the elements in the defect during the course of analysis were also documented in this paper.

We present experimental results of IC package decapsulation carried out using Ar and O2 gas mixture remote plasma generated by atmospheric microwave plasma needle (“a-MPN”). Depth etch rate of up to 6.5 µm/min and volume etch rate of up to 0.1 mm3/min were shown to be obtained by a-MPN process operated at 15 W microwave power. SEM imaging suggested no damage to the bonding wire, pads, or passivation.

Wet Chemical Deprocessing is one of the techniques in exposing embedded structures in an integrated circuit (IC). Layers of the die from the passivation to silicon substrate can be selectively etched using this technique. From series of evaluations conducted, it was discovered that there are silicon damage sites that are induced during wet chemical deprocessing. Their physical attributes are almost identical to the attributes of electro-static discharge (ESD) defects. It only differs in the locations where they occur. ESD defects are expected near the edges of the transistors’ gate channel where high electric fields are present while deprocessing artifacts are observed at the center of the gate channel. Deprocessing artifacts are represented by mechanically induced damage sites in the silicon substrate. These mechanical damage sites manifest in the form of silicon pits, voids, slits and fractures as a result of tensional or shearing stresses in the silicon substrate when the polysilicons separate from the silicon substrate. If deprocessing artifacts are not well understood by the analysts then these can be mistakenly reported as ESD or fabrication defects.

Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight mechanical or thermal boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces can be divided into two modification approaches. The back side approach is typically done for die level analysis by de-processing through encapsulated mold compound and silicon gaining access to the silicon transistor level. On the other hand, the front side approach is typically used for package level analysis by de-processing the ball grid array (BGA) and package substrate layers. Both of these local de-processing approaches can be done by using the conventional Laser Chemical Etching (LCE) platforms. The focus of this paper will be to investigate a front side modification approach to provide substrate material removal solutions. Process details and techniques will be discussed to gain access to metal signals for further failure analysis and debug. A pulse laser will be used at various processing stages to de-process IC package substrate materials.

This paper presents two new methods using potassium hydroxide (KOH) as a wet etch technique to successfully stop on gate oxide and find the submicron gate oxide failures that correspond to failure response sites. Applications of this new technique to submicron gate oxide failures on both planar and deep trench MOSFET devices are reported in this paper.

This work presents a novel method of continuous improvement for faster, better and cheaper TEM sample preparation using Cut Look and Measure (CLM). The improvement of the process is executed by operational monitoring of daily beam conditions, end products, bulk thickness control, recipe usage and tool running time. This process produces a consequent decrease in rework rate and process time. In addition, it also increases throughput with better quality TEM samples.

Prior to x-ray tomography, cylindrically-shaped samples are obtained using an innovative milling strategy on a Plasma-FIB. The method presented consists of tuning the ion dose as a function of pixel coordinates along with optimization of the scan geometries, drastically reducing the preparation time and significantly improving the overall workflow efficiency.

Defect localization has become more complicated in the FinFET era. As with planar devices, it is still generally possible to electrically isolate a failure down to a single transistor. However, the complexity of certain FinFET devices can lead to ambiguity as to the exact physical location of the defect. The default technique for isolating the defect location for this type of device is to start with a plan view S/TEM lamellae. Once the defect is located in plan view, the lamellae can be converted to cross-section (if necessary) for further characterization. However, if the defect is not detectable in plan view S/TEM analysis, an alternative approach is to examine the device in cross-section along either the x- or y- axis. Once the defect is located in the initial cross-sectional lamellae, it can be converted to the orthogonal axis if the initial cross-sectional lamellae did not provide adequate information for characterization. However, in converting a cross-sectional lamellae to the orthogonal axis, the initial lamellae must be exceedingly thin due to the dimensions of devices on 1x nm FinFET technologies, else other structures on the sample can obscure the view in the S/TEM. This can lead to structural integrity (warping) issues for the converted lamellae. In this paper, a novel solution to the warping issue is presented.

An enhanced back-side deprocessing recipe has been established with an additional heat step compared to previous methods. This enhanced recipe reduces overall deprocessing time by 70%. The edges with higher silicon thickness can be polished simultaneously. This recipe has proved repeatable and successful across different technology nodes and die sizes.

Focused Ion Beam is widely used in semiconductor industry for critical applications such as TEM sample preparation and circuit edit. In this paper, we introduce an automated failure analysis technique for high precision polishing at the wafer level. Using FIB, it is possible to precisely mill at a region of interest, capture images at the region of interest simultaneously and cut into the die directly to expose the exact failure without damaging other sections of the specimen.

Silicon’s index of refraction has a strong temperature coefficient. This temperature dependence can be used to aid sample thinning procedures used for backside analysis, by providing a noncontact method of measuring absolute sample thickness. It also can remove slope ambiguity while counting interference fringes (used to determine the direction and magnitude of thickness variations across a sample).

This paper demonstrates a new de-process flow for MEMS motion sensor failure analysis, using layer by layer deprocessing to locate defect points. Analysis tools used in this new process flow include IR optical microscopy, thermal system, SEM and a cutting system to de-process of MEMS motion sensor and successful observation defect points.