The aim of this work is to disclose about the difficulties of handling quasi-static transition failures and propose one possible strategy to detect and locate them in a failure analysis test environment with the most appropriate fault localization technique.

Traditional fault based scan ATPG stuck-at, transition-delay and small-delay defect and custom multi-transition fault model based patterns have been used as the primary DFT scan test content for many years to guarantee zero defects on automotive designs. Continued analysis to reduce DPPB on multiple automotive designs confirmed presence of subtle cell-internal defects that were not getting screened out using the traditional set of fault model based patterns and, motivated us to evaluate and integrate defect-oriented cell-aware tests on automotive designs. In this paper, we will first discuss the cell-aware pattern generation flow followed by the enhanced test program flow that was used to screen and identify unique cell-aware only failures from a new product introduction design. Later, we will review the deep-dive findings from the first unique cell-aware failure on a new design. ATE silicon characterization, failure analysis findings and ATPG simulation along with CMOS transistor level explanation of how cell-aware transition-delay patterns were more effective in screening out the defective unit when compared to traditional transitional-delay patterns will be discussed in detail.

The success of failure analysis and related investigations rely on the quality of information made available to the investigating team. When die level traceability (DLT) is implemented on the product, the actual location of a particular unit in the wafer and all the available data can be traced back and pieced together to reveal insights on the possible root cause( s). The data for the specific unit can be determined, then analyzed and compared with the lot distribution to check for any information that could help the analyses and investigations. With access to the original data, a failing unit can be investigated to determine which data have changed which can prove essential to the direction of failure analysis approach. Four case studies will be discussed to demonstrate how DLT enabled fast, accurate and detailed root-cause identification leading to effective corrective and preventive actions.

As devices shrink, mitigating off-state power consumption has become a major concern for dynamic random access memory (DRAM) product development. The interface trap induced reduction of the retention time of DRAM cells has become increasingly critical due to aggressive device shrinkage. In this paper, the influence of reliability evaluation after device manufacturing on the number of interface traps in buried-channel-array-transistors and the optimal H 2 annealing temperature were investigated for the reduction of trap-induced leakage currents that cause retention time degradation in DRAM cells. This study is expected to solve the problem of retention time and off-state power consumption caused by interface traps and to be utilized as a cornerstone for next-generation DRAM development.

This paper presents a user-defined fault model (UDFM) that accounts for silicon behaviors that cannot be explained using traditional stuck-at and transition delay fault models. The new model targets cell-internal faults but does not require time-intensive SPICE simulations because it operates at the logic level. As added benefit, error logs collected using UDFM patterns (instead of traditional models) can be used to generate diagnostic callouts with improved resolution. A workflow that effectively achieves this is presented in the paper along with three case studies that demonstrate the usefulness of the proposed method.

For unique single failures, which tend to be the case in customer return and reliability failures, selecting another sample or performing root cause deconvolution is not an option, and if diagnostic tests are not conclusive, it becomes necessary to extend the effectiveness of automatic test pattern generator (ATPG) diagnosis in order to determine the failure mechanism. This paper proposes a way to improve resolution using single-shot logic and high-resolution targeted patterns. Two cases are presented to demonstrate the approach and show how it performed on actual failing units.

This paper presents a new method for improving the quality and effectiveness of scan-based tests. The method, called statistical diagnosis, leverages defect likelihoods learned from analyzing populations of failing die instead of analyzing each die independently as traditionally done. The method was validated in a large silicon study that showed significant improvement in diagnosis resolution with minimal impact on diagnosis accuracy. Statistical diagnosis, as the paper explains, can also be used to predict or identify the dominant defect mechanism in low yielding wafers.

This paper presents a machine learning approach that uses genetic algorithms to optimize test program timing sets based on first silicon. The method accounts for test hardware differences, discrepancies in silicon processes, and IO pin interdependency. The general theory and implementation are covered in detail and the capabilities of the method, in terms of false fail discovery, elimination, and failure debug, are demonstrated using actual product test cases.

This case study shows that wafer notch orientation can have a significant effect on defect capture rates obtained during defect inspection. The discovery was made when a review of historical data showed that the relationship between defect densities and yield varied greatly for different products in regard to a terminal metal layer. A product design analysis on the affected layer revealed that a majority of metal lines were oriented the vertical direction in one product and in the horizontal direction in the other. It was then shown that this difference could be offset by rotating the wafer in the defect scan tool, which resolved the data discrepancy. This work highlights the importance of considering the orientation of metal lines in each layer when creating a new defect scanning recipe.

We have adopted various defect detection systems in the front stage of manufacturing in order to effectively manage the quality of flash memory products. In this paper, we propose an intelligent pattern recognition methodology which enables us to discriminate abnormal wafer automatically in the course of NAND flash memory manufacturing. Our proposed technique consists of the two steps: pre-processing and hybrid clustering. The pre-processing step based on process primitives efficiently eliminates noisy data. Then, the hybrid clustering step dramatically reduces the total amount of computing, which makes our technique practical for the mass production of NAND flash memory.

Cell aware diagnosis identifies defects within the standard cell as opposed to traditional layout aware diagnosis that identifies the failing standard cell or the area between two standard cells. In a mature technology dominated by random defects, cell aware results pinpoint the cell internal layer drastically reducing the turnaround time for failure analysis. This paper describes a method to enable cell aware diagnosis in a foundry environment, perform a volume diagnosis analysis with RCAD (fail mode pareto) and drive failure analysis with a quick turnaround time for a 14nm customer chip.

Low-K dielectric adhesion problems were observed at M1 and M2 levels during thermal cycling of a flip chip product. Nano-indentation of simple BEOL test structures was used to determine the relative strength of the various interfaces in the BEOL stack. It is observed that the weakest adhesion is associated with the initial stages of the SiCOH low-K dielectric deposition. Adhesion loss related to the SiCN etch stop deposition is not observed.

X-ray imaging for both Failure Analysis and In-line Inspection has been utilized widely in the semiconductor industry, especially for surface mount device applications. During the investigation of total ionizing dose (TID) induced degradation of logic ICs with bulk FinFET technology, we observed that the degradation is mainly in the form of an increase in I/O leakage and IDDQ . Using filters during radiation was shown to impact TID. Failure Analysis was performed to localize the excessive current in both I/O leakage and IDDQ.

Scan-based test has been the industrial standard method for screening manufacturing defects. Scan chains are vulnerable to most manufacturing defects and process variations. Therefore, chain failures diagnosis is critical for successful yield learning. However, traditional chain diagnosis requires failing masking patterns to identify faulty chains and their fault types for designs with test compression. In other words, it cannot diagnose the chain failures which don't fail the masking chain patterns. Unfortunately, advanced FinFET technologies with more manufacturing challenges and higher process variations may result in more subtle chain timing failures which can't be detected by chain masking patterns. In this work, we present a new debugging methodology, which combines chain diagnosis and tester-based test to effectively diagnose such intermittent chain failures. The proposed methodology is validated on silicon data for one modern large SOC design and successfully identified all scan cells with hold-time issues, which were validated by STA with corrected models. The subsequent mask fixes for these identified hold-time violations resolved this yield issue and dramatically improve the yield.

Many fabless customers do not share the design information such as LEF/DEF (Library Exchange Format and Design Exchange Format), design netlist, and test program information with foundries because they contain proprietary IP. Determining the root-cause of defects on such products only based on Sort test results and no scan diagnostics [1] for logic chips can be quite challenging. This paper presents a new layout pattern analysis methodology to isolate the failing weak layout structure using only the sort test results and the product GDS layout.

Laser Assisted Device Alteration (LADA) or Soft Defect Localization (SDL) is commonly used to root cause device marginality due to functional or structural failures. At a high level, LADA involves setting the device under test (DUT) at its marginal state and using focused near infra-red laser beams to perturb sensitive circuitry [1]. Scanning the focused laser beam over the die can be a long and time-consuming process. In this paper, two LADA cases are presented, which involve a parametric measurement failure while running a dynamic ATE test. Using LADA technique, these two cases were root caused. These two cases also explain how a parametric measurement-based LADA can be setup on ATE, as well as a synchronization method independent of vectors in a pattern. Synchronization was necessitated in the 2nd case due to the asymmetric test program loop, as well as the long test program cycle time. There are many factors which impact LADA turnaround time and it can take anywhere between few seconds to one day. The two major factors are the size of the Area of Interest (AOI) and test program cycle time. Test program cycle time influences the laser “dwell time” for LADA. Dwell time, in simple terms, is the total time the laser is parked at each pixel. The laser can also be synchronized with the test program cycle, keeping the two always in phase. This is explained in Case 2, where LADA synchronization was implemented, and the analysis was successfully completed in time, even though the test cycle time was very long.

High quality and reliability are paramount for automotive and other high grade commercial applications. The implementation of scan testing including stuck-at, transition, IDDQ, bridging and cell-aware patterns have all been targeted at reducing the number of defective parts being shipped. These techniques are not always sufficient to achieve sub defective parts per million (DPPM) quality levels. This paper presents a recurring failure mechanism that was encountered on an automotive device and the subsequent efforts to expand upon existing testing methodologies to effectively screen the defective devices using a delta IDDQ method with specific logic inputs and outputs. In effect, this new testing becomes a cell-aware delta IDDQ targeting one specific input condition that was implemented in production with limited test time overhead.

This paper discusses a creative manual diagnosis approach, a complementary technique that provides the possibility to extend Automatic Test Pattern Generation (ATPG) beyond its own limits. The authors will discuss this approach in detail using an actual case – a test coverage issue where user-generated ATPG patterns and the resulting ATPG diagnosis isolated the fault to a small part of the digital core. However, traditional fault localization techniques was unable to isolate the fault further. Using the defect candidates from ATPG diagnosis as a starting point, manual diagnosis through fault Injection and fault simulation was performed. Further fault localization was performed using the ‘not detected’ (ND) and/or ‘detected’ (DT) fault classes for each of the available patterns. The result has successfully deduced the defect candidates until the exact faulty net causing the electrical failure was identified. The ability of the FA lab to maximize the use of ATPG in combination with other tools/techniques to investigate failures in detail; is crucial in the fast root cause determination and, in case of a test coverage, aid in having effective test screen method implemented.

Contamination and particle reduction are critical to semiconductor process control. Lots of failure analysis had been focused on finding the root cause of the particle and contamination. The particle and contamination effect were also easily found in circuit probing (CP) process, and therefore induced yield loss and wafer scrap. In the first part of this paper, an oven contamination case was studied. The second part of this paper focus on oven contamination monitoring. In the beginning, a die flying failure was papered at the stage of blue tape and die sawing. This event clearly indicated bad adhesion between die and plastic tape. This bad adhesion was suspected to be a particle/contamination layer formed on bad die surface. Three failure analysis (FA) approaches were performed to find out the root cause. The SEM/EDS result identified the main elements of big particle, but that is insufficient to identify the root cause. The OM/FTIR, however, showed the contamination may be related to polydimethylsiloxane (PDMS). The last failure analysis was the time of fly Secondary Ion Mass Spectrometer (TOF-SIMS), the result confirmed that there was a thin PDMS layer formed on the contaminated bad die surface. The high temperature CP process induced PDMS is believed to be the contamination root cause. In order to prevent the oven contamination event, a methodology based on contact angle and wettability of Si matrix sample was set up for regular monitor in oven operation. The details of contact angle test (CAT) sample preparation, measurement and analysis results were also discussed in this paper.

Rapid and accurate root cause analysis of the defect contributes to improvement in yield and quality in semiconductor manufacturing system. In particular, imperfection of final test can cause major problems for customers, so analysis on root cause of final test failure is important activity for high quality. It can be started with finding first test data which is highly correlated with final test failure. However, it is difficult to analyze the correlation of first test data and final test failures because the first test is made up of hundreds of test items, and the data also show non-parametric characteristics with extreme outlier. In this study, Kolmogorov-Smirnov test (K-S test), which is a non-parametric test method, is statistically applied to the first test data. The K-S test is intuitive and descriptive, which makes it easy to analyze the root cause. And K-S test showed a performance improvement compared to t-test statistic, which requires a normal distribution assumption. Therefore, our data mining approach can help analysis to improve yield and quality of mass production with highly scaled devices.