Analog Devices Inc. (ADI)’s Radar Receive Path Analog Front End Amplifier (AFE) with a 0.18um 6-metal Fab Process has failures related to Power-Down and Scan test parameters which were endorsed for Failure Analysis. Fault localization is quite challenging because it involves 6 metal layers. This has been resolved with the availability of Synopsis Avalon software with capability to convert the complete Cadence schematics and layout that is usable for Failure Analysis, through cross-mapping with the fault localized area-of-interest (AOI) on the actual reject part with the die schematics and layout, and identifying the failing component and circuit block. This leads to the creation of the failure model related to the reported failure mode and the determination of the appropriate failure mechanism related to fabrication defects between the adjacent metallization layers and defects on between the polysilicon and substrate layer. This helps speed up the FA Cycle Time and achieve an accurate failure mechanism, which later resolves the fab defect issue with the Fab process owner.

Failure localization is one of the vital processes in the field of failure analysis. However, as newer fabrication processes emerge and demand for smaller transistors keeps on increasing, the complexity of failure analysis fault isolation involving micro-probing also increases along with the challenges on fault isolation equipment such as limited magnification and susceptibility to vibrations. In this paper, the capability of Focused Ion Beam (FIB) to perform circuit edit was utilized along with Avalon CAD navigation to pinpoint the location of the defects without the need of micro-probing while doing fault isolation. Results showed that through this technique, physical defect locations were successfully identified in three different case studies.

Power MOSFETs are electronic devices that are commonly used as switches or amplifiers in power electronics applications such as motor control, audio amplifiers, power supplies and illumination systems. During the fabrication process, impurities such as copper can become incorporated into the device structure, giving rise to defects in crystal lattice and creating localized areas of high resistance or conductivity. In this work we present a multiscale and multimodal correlative microscopy workflow for the characterization of copper inclusions found in the epitaxial layer in power MOSFETs combining Light Microscopy (LM), non-destructive 3D X-ray Microscopy (XRM), Focused-Ion Beam Scanning Electron Microscopy (FIB-SEM) tomography coupled with Energy Dispersive X-ray Spectroscopy (EDX), and Transmission Electron Microscopy (TEM) coupled with Electron Energy Loss Spectroscopy (EELS). Thanks to this approach of correlating 2D and 3D morphological insights with chemical information, a comprehensive and multiscale understanding of copper segregations distribution and effects at the structural level of the power MOSFETs can be achieved.

The challenges keep rising for fault isolation and failure analysis (FIFA) for the advanced semiconductor devices fabricated via integrated processes. Perceiving that defects randomly occurred during IC manufacturing contribute primarily to the device failures in comparison to those caused by harsh service environmental, we focus our efforts on fixing the defect issues in the processes, expecting a significant portion of the device failures may be prevented. A case study here demonstrates the procedure for fixing an inline defect issue via improving tool maintenance for the chemical-mechanical polishing (CMP) process. Through a correlative physical and chemical analysis down to atomic scale, a 10 nm diamond particle and a 10 nm metallic debris damaging one of the metal interconnect layers were defined. The analysis led to pinpointing the issue to a metal CMP process. By examining the process operation and the tool configuration, we located the diamond-missing sites on a pad-conditioning disk made with embedded diamond grits in a metal matrix. Preventive countermeasure were implemented to avoid the same defect recurring via resetting the disk life and maintenance.

Static random-access memory (SRAM) is a type of device that requires the highest reliability demands for integration density and process variations. In this study, we focus on single bit cell SRAM failures. These failures can be categorized as Hard bit cell failure, where bit cells fail the read or write operation under both higher and lower supply voltages, and Soft Bit cell failure, where failures occur at either higher or lower voltage. The analysis on SRAM Soft failure is further divided as VBOX High and VBOX Low failure, which depends on the failure mode supply voltage. With transistor dimensions continuously shrinking, the analysis of SRAM errors imposes tremendous challenges due to their small footprint. In this paper, a thorough failure analysis procedure is described for solving an SRAM yield loss issue. Different analysis techniques were applied and compared to narrow down the failure to the final root cause, including nanoprobing, Focus Ion Beam (FIB) cross-section, Scanning Spreading Resistance Microscopy (SSRM), Transmission Electron Microscopy (TEM), Electron Energy Loss Spectroscopy (EELS), Scanning Capacitance Microscopy (SCM), and stain etch.

This paper presents a root cause analysis case study of defective Hall-effect sensor devices. The study identified a complex failure mode caused by chip-package interaction, which has a similar signature to discharging defects such as ESDFOS. However, the study revealed that the defect was induced by local mechanical force applied to IC structures due to the presence of large irregular-shaped filler particles within the mold compound. Extensive failure analysis work was conducted to identify the failure mode, including the development of a new backside analysis strategy to preserve the mold compound during IC defect localization and screening. A combination of different failure analysis techniques was used, including CMP delayering, PFIB trenching, SEM PVC imaging, and large area FIB cross-sectioning. The study found that the mold compound of the package caused thermos-mechanical strain onto the silica filler particle due to epoxy shrinkage during the molding process. Additionally, extra-large, irregularly shaped filler particles (called twin particles), located on top of the chip surface, can cause locally high compression stresses onto the IC layers, initiating cracks in the isolation layers under certain conditions forming a leakage path over the time. Thermo-mechanical finite element analysis was applied to verify the mechanical load condition for these large irregular-shaped filler particles. As a result, an additional polyimide layer was introduced onto the IC to mitigate the mechanical stress of mold compound particles to avoid this failure mode.

Completion of failure analysis (FA) cases require a lot of expensive equipment and tools. Equipment Management System (EMS) is a must to safeguard the equipment from being down/damaged due to uncertified/untrained and high number of users and to avoid high repair cost of the FA laboratory equipment. The purpose of this paper is to present the RFID-based equipment management system for failure analysis laboratory equipment which has the capability to limit the equipment usage to authorized and certified users, locks and unlocks the equipment, and controls the real-time status of the equipment.

Failure Analysis (FA) uses combinations of a multitude of methods to identify and localize failures in semiconductor devices. The performance or efficiency of a FA lab is often measured by throughput or the total time needed to complete an analysis. These KPIs (Key Performance Indicators) can be optimized, but sequences of executed methods might be long and, therefore, hard to understand and optimize. Processes executed in an ad hoc manner might block each other causing long queues for specific tools and overloading specialists working with them. These and other factors can lead to a significant decrease in lab performance. In this paper, we propose an approach to analyzing FA processes with a focus on Internal Physical Inspection (IPI) jobs. Specifically, we use machine learning and statistical methods to estimate (a) the workflow that engineers follow while completing IPI jobs and (b) the duration of each operation executed in the workflow. Our approach starts with data extraction and preprocessing, aiming at extracting features characterizing the workflow, like the package or technology of a sample, as well as providing information about the complexity of each task, thus, allowing us to predict their duration. The resulting tool allows lab management and team leads to analyze the execution of IPI jobs and optimize them. Moreover, the information provided by the tool can be used in automated scheduling methods providing recommendations to FA engineers about sequences of jobs improving utilization of the lab’s resources.