One of the foremost challenges in the field of SiC MOSFET failure analysis is the effect of thermally modified mold compound on the decapsulation process. The extended total etch time that thermal modification imposes on the process of wet chemical decapsulation has created a niche for new techniques to fill. This paper focuses on use cases for the JIACO microwave-induced plasma (MIP) etching system and how to best optimize the tool’s settings to facilitate time-efficient decapsulations. The words and data that follow aim to present what has been determined to be a successful alternative for the decapsulation of thermally modified Si and SiC power devices when wet etches prove to be ineffective.

We present a study of dislocation conductivity under forward bias in p-GaN/AlGaN/GaN heterojunctions on a GaN-on-Si substrate, which are part of every p-GaN HEMT structure. Conductive atomic force microscopy (C-AFM) is combined with structural analysis by scanning transmission electron microscopy (STEM) and defect selective etching (DSE). The density of conductive TDs was found to be 5 × 10 6 cm -2 , using semi-automatic measurements to gather larger statistics on a delayered HEMT sample. IV measurements show a shift in turn-on voltage at the leakage positions. To characterize the type of the conductive TDs, DSE with a KOH/NaOH melt was used. Three distinct etch pit sizes were observed after 5 s etch time, with large, medium and edge pits according to STEM characterization seemingly corresponding to screw, mixed and edge TDs, respectively. However, characterization by DSE etch pit size alone was found to be unreliable, as STEM TD typing of seven conductive TDs using two-beam diffraction conditions revealed mostly pure screw and mixed-type dislocations with medium-sized etch pits as origin of the observed leakage current. Our work highlights the limitations of DSE as a characterization method and recommends additional validation by STEM for each new material system, investigated layer, and etching setup. The implications of finding conductive TDs with screw-component under low forward bias conditions on device behavior and the limitations of the C-AFM method are discussed. Based on the results, it is not anticipated that the identified conductive TDs will have a substantial effect on a GaN HEMT device. Overall, this study provides important insights into the electrical properties of TDs and offers useful recommendations for future research in this area.

An innovative method of characterizing p/n junctions and finding defects in SiC MOSFETs is discussed. First, a baseline technique is considered, which involves OBIRCH analysis of shorting paths after etching off the surface metal. The resolution, however, is not satisfactory. Top surface EBIC and EBIRCH results are then presented. Single-probe imaging with EBIC on gates with a 25 kV SEM (Scanning Electronic Microscopy) is shown to be able to image sub-surface depletion zones in the sample. Further measurements by EBIRCH isolated the precise spot of the defect.

III-V power electronic devices are a growing industry as electric vehicles (EVs), power-demanding servers, and other high-power electronics become more prominent. The design of these devices can alter a failure analysis lab’s process flow typically used on traditional silicon-based logic devices. One such obstacle is backside fault isolation (FI) through highly doped silicon wafers used in GaN-on-Si technologies. Backside fault isolation is critical for many electrical failure analyses so finding several approaches to enable this technique that fits current FA flows is desirable. Chemical and Focused Ion Beam (FIB) based approaches have been used to enable backside FI [1], [2]. This paper considers a plasma-based approach with two separate machines, a Microwave Induced Plasma spot etcher and a chamber based Reactive Ion Etch (RIE). Both utilize a Fluorine-based chemistry which is highly selective to the silicon vs the underlying GaN. The etches are used to selective remove the silicon to form a window to the underlying GaN material. Subsequent backside FI analyses are successfully followed by several other analyses.

This work reviews the capabilities of cathodoluminescence spectroscopy to monitor several key performance indicators in GaN-based High Electron Mobility Transistors (HEMTs) manufacturing. In particular, high throughput threading dislocation (TD) density measurements in the 10 8 -10 9 cm -2 range are presented, together with dislocation type discrimination capabilities. Beyond these applications, other relevant topics such as buried AlGaN layers composition and Mg dopant concentration for normally off devices are introduced.

Threading dislocations are a feature of all current GaN-based power devices and are speculated to impact their performance and reliability. The aim of this study is to cross-correlate electrical and physical characterization of dislocations using electron beam induced current (EBIC), electron channeling contrast imaging (ECCI), and transmission electron microscopy (TEM) analysis techniques. Sample preparation steps such as deposition and etching of markers via focused electron beam (FEB) and focused ion beam (FIB) turned out to be decisive for successful characterization. We describe in detail various approaches required for successful cross-correlation and present appropriate workflows.

Insulated Gate Bipolar Transistors (IGBT) and silicon carbide (SiC) based MOSFETs have become the predominantly used power semiconductors in particular in automotive applications. For failure analysis of such devices, site-specific access to subsurface fault sites is required, as is understanding their construction and junction profiles, and how the device turns on. We have applied focused ion beam-scanning electron microscopy (FIB-SEM) tomography to visualize inner structure and dopant distributions of an IGBT and of a SiC MOSFET in three dimensions (3D). Such 3D data can be used to complement 2D electron beam induced current (EBIC) measurements obtained at site-specific FIB cross-sections in these devices.

For device qualification in harsh environments (space, avionic and nuclear), radiation testing identifies the sensitivity of the devices and technologies and allows to predict their degradation in these environments. In this paper, the analysis of the electrical characteristics and of the failure of a commercial SiC MOSFET after a Single Event Burnout (SEB) induced by proton irradiation are presented. The goal is to highlight the SEB degradation mechanism at the device and die levels. For failed devices, the current as a function of the drain-source bias (VDS) in off-state (VGS=0V) confirms the gate rupture. For the die analysis, Scanning Electron Microscopy (SEM) investigations with energy-dispersive X-ray spectroscopy (EDX) analysis reveals the trace of the micro-explosion related to the catastrophic SEB inside the SiC die. With a fire examination, similar to a blast, the SEM analysis discloses damages due to the large local increase of the temperature during the SEB thermal runaway, leading to the thermal decomposition of a part of the SiC MOSFET and the combustion with gaseous emissions in the device structure.

This paper describes a backside approach methodology for sample preparation, fault localization and physical defect analysis on p-GaN power HEMT electrically stressed in DC voltage surge and AC switching mode. The paper will show that preparation must be adapted according to the defect position (metallurgy, dielectric layers, epitaxy, etc.) which depends on the type of stress applied. In our life-operation mode amplified electrical stress reliability study, the failure analysis will help us to reveal the weakest parts of the transistor design in relation to the type of applied stress. The failure analysis presented in this paper is composed of electrical characterization, defect localization with PEM and LIT, FIB Slice&View, TEM analysis and frontside conductive AFM after a deep HF.

Atom probe tomography is used to characterize the 3D Al dopant distribution within the gate diffusion region of a deconstructed SiC n-channel junction field effect transistor. The data reveals extensive inhomogeneities in the dopant distribution, which manifests as large Al clusters - some of which are ring-shaped and indicative of dopant segregation to lattice defects in the SiC. The presence of defects in the SiC is confirmed by transmission electron microscopy of an identical region. Factors that may impact the atom probe data quality and consequently complicate data interpretation are considered, and their severity evaluated. The possible origin of the lattice defects in the SiC and the corresponding implications for device performance and reliability are also discussed. Overall, the utility of atom probe tomography and correlative transmission electron microscopy for revealing potential failure mechanisms of next-generation semiconductor devices is demonstrated.

A commercially available 4H-SiC power device and a GaN on SiC HEMT were examined with Ga-FIB sectioning and various junction analysis techniques. The impact of Ga-FIB on the electronic properties of such power devices is observed to be less significant than anticipated. A field of view was FIB-milled into the structure, exposing a row of devices. In this window, p/n junctions were evaluated by Passive Voltage Contrast (PVC), Electron Beam Induced Current (EBIC), and Kelvin Force Probe Microscopy (KFPM). Results showed excellent fidelity to expectations and each technique brought out new insights. In further work, the gate voltage was varied and the changing of depletion zones upon device turn-on was observed. This work: 1) Demonstrates complete sufficiency of Ga-FIB cross sections for regular cross-sectional work. 2) Demonstrates a novel method for investigating junction properties from Ga-FIB sections of power devices which largely leaves the rest of the device intact. 3) Provides some assurance that the Ga-FIB does not severely impact the evaluation of junction properties in some power semiconductors. 4) Points to alternative mechanism for device turn-on.

Power devices technology and in particular devices based on 4H-SiC require a thick metal layer in top to make a source contact and on the backside to make a drain contact. These metal layers are the main problem for fault isolation activities. Up today, many fault isolation techniques do not allow for results, and it is mandatory to remove this layer before performing them. During the metal removal on wafer there is a high probability of damaging the sample or breaking the wafer, especially if the latter is very thin. In this analysis we show a methodology that allows fault isolation analysis, performed on wafers with metal layers, preventing the risks of sample damage induced from preparation.