Electrostatic discharge (ESD) can easily damage the nanoprobes used in the failure analysis of semiconductor devices. Nanoprobes with tips that have radii of curvature of a few nanometers are especially sensitive to ESD damage, because applying even modest electrical potentials leads to high electrical fields at the tip of the sharp probe. ESD damage has been used as an umbrella explanation to explain a variety of probe failures and undesirable tip features, but due to the stochastic nature of these events, its effect on nanoprobes has hitherto not been well documented. This paper describes the effect that ESD events have on the tip profile of nanoprobes and describes best practices so that such events can be more readily diagnosed and prevented by nanoprobe users. The likelihood of an ESD event occurring can be reduced by eliminating potential differences between users and the probes and by regulating laboratory humidity levels.

Lock-in thermography (LIT) is a firmly established and powerful technique for IC defect localization. The standard approach is to detect and analyze the device temperature fluctuation between two bias conditions using an infrared thermal imaging camera and check for any anomalous heat response. For the most straightforward setup, these bias conditions would be achieved by the modulation of a supply voltage provided by the LIT system. This allows for synchronization to the internal camera frame rate. In addition to this method, the ability to provide an external trigger may be an option, as it is for the ELITE system by Thermo Fisher Scientific. This expands the LIT arena to failures that may only be observable by, for example, setting different register contents at a constant supply voltage. Though IC testers can be used to provide the stimulus and a trigger signal for these situations, often a simpler, more compact solution would be beneficial for the failure analyst. This paper presents such an alternative: the application of a low-cost, USB-based module which can emulate various communication protocols (for example, I 2 C, SPI) while providing a synchronized timing pulse to externally trigger the ELITE, thus facilitating dynamic LIT investigations. The efficacy of this solution is demonstrated by a case study in which dynamic LIT produced a single hot spot at the defect site that was undetected by the voltage modulation approach.

The present paper provides an inexpensive method to assess the surface charge density variance directly in capacitive MEMS switches. It was found experimentally that the charge variance decay is directly associated with the presence of ambient humidity, which increases the dielectric film surface conductance. This result is qualitatively confirmed with the aid of interdigitated comb structures, where the same behavior was detected.

This paper has been withdrawn at the request of the author.

Passive voltage contrast (PVC) is a well-known fault isolation technique in differentiating contrast at via/metal/contact levels while focused ion beam (FIB) is a destructive technique specifically used for cross sectioning once a defect is identified. In this study, we highlight a combination technique of PVC and progressive FIB milling on advanced node fin field-effect transistor (FinFET) for root cause analysis. This combo technique is useful when applied on high-density static random access memory (SRAM) structure, especially when it is difficult to view the defect from top-down inspection. In this paper, we create a FA flow chart and FIB deposition/milling recipe for SRAM failure and successfully apply them to three case studies.

Photon Emission Microscopy (PEM) analysis is one of the most common used FA techniques to identify the root cause of failures within ATPG scan logic due to its ease of setup and less invasive nature. While conducting photon emissions, the device is made to operate in the fail mode by running a production test vector to look for anomalous emissions or hot spots that could narrow down the area of interest (AOI) for subsequent Physical Failure Analysis (PFA). However, if there is no clue from emission analysis in the case of a hard failure with no sensitivity to voltage, frequency, or temperature, FA debug will be challenging. This paper shows how PEM analysis success may be further improved through logic state circuit study using a DFT ATPG diagnostic platform. Logic state truth table and its relative test pattern will be built based on the diagnostic data using in-house scripts, and the test program can then be changed to the required condition of the circuitry. With the altered logic state, new emission data can be collected, which could potentially reveal new clues to the investigation.

The importance of charging damage grows as the IC industry continues downward scaling. It was found that electrical test on metal pad to check contact failure, layer connection and resistance caused charging damage as serious as plasma charging. As for the side effect of it, DC charge is accumulated on the metal TEG, which causes some failure such as incomplete etch problems in the next metal fabrication. This paper provides that charge effect on metal surface is able to be verified by Scanning Capacitance Microscope (SCM). SCM has been used to analyze carrier trap on semiconductor layer in 2D mapping image as well as dopant distribution. In this paper, we will present SCM as more effective and sensitive than contact based DC-EFM (Electrostatic Force Microscope) and verify how to detect the charge on the surface of metal with a physical model based on a parasitic capacitance. It is possible to analyze MIM (Metal-Insulator-Metal) structure because permittivity of insulator is varied like MOS (Metal Oxide Semiconductor) for induced dielectric dipole polarization. Even though it is required to deposit additional insulator layer on a metal, it is highly beneficial to inspect charge effect during post-processing.

DRAM is a type of memory that stores each bit of data in a capacitor cell, leakage current is a very important electrical parameter to retain data. Therefore, larger cell capacitance and smaller leakage current have been regarded as key factors in continuous shrinkage of DRAM. Generally, gate induced drain leakage (GIDL) and junction leakage of cell transistor (CTR) are well-known, but our approach is focused on retention failure by bulk trap. In order to electrically observe the influence of bulk trap, we used the adjacent gate of CTR to control electron migration. Results show that there are many failure cells due to bulk trap, and dimension shrinkage accelerates this failure. Consequently, balancing among electrical bias point and transistor manufacturing process should be carefully considered with bulk traps.

In wafer fabrication, silicon defects on the substrate directly affect the yield of the wafer. In this paper, we will study and discuss a chemical delayering and delineate method for silicon defects in wafer fabrication using Secco etch. It is well-known that during delayering process of wafer, the removal of polysilicon (Poly-Si) layer is very difficult, especially for the wide-layer polysilicon (Poly-Si) which is difficult to completely remove with HF acid solution. We introduce a chemical recipe to fast delayer polysilicon layer completely before delineating silicon defects on silicon substrate using Secco etch. Those skilled in the art could be experiment within half an hour to get analysis results. It saves time and improves operational efficiency. Moreover, based on the experimental results we think that it is possible to identify the root cause according to the shapes of silicon defects using Secco etch.

Failure analysis engineers apply a combination of conventional static fault isolation tools such as OBIRCH, PEM, or lock-in thermography (LIT) to detect simple short defects. However, if the defect is located in a complex circuit, analysis can be more challenging. Laser voltage probing and imaging (LVx) is widely used but will have difficulty in localizing a defect in the backend layers. The combination of LVx and LIT can resolve complex short cases that either of these techniques alone cannot easily do. This paper introduces the thermal effect of LVx and applications of LIT for functional analysis, and it describes and provides case histories for complementary fault isolation procedures for detecting defects in metal layers and transistors.

Currently, wire bonding is still the dominant interconnection mode in microelectronic packaging, and epoxy molding compound (EMC) is the major encapsulant material. Normally EMC contains chlorine (Cl) and sulfur (S) ions. It is important to understand the control limit of Cl and S in the EMC to ensure good Au wire bond reliability. This paper discussed the influences of Cl and S on the Au wire bond. Different contents of Cl and S were purposely added into the EMC. Accelerated reliability tests were performed to understand the effects of Cl, S and their contents on the Au wire bond reliability. Failure analysis has been conducted to study the failure mechanism. It is found that Cl reacted with IMCs under humid environment. Cl also caused wire bond failure in HTS test without moisture. On the other hand, the results showed that S was not a corrosive ion. It was also not a catalyst to the Au bond corrosion. Whilst, high content of S remain on the bond pad hindered the IMCs formation and caused earlier failure of the wire bond.

Analog fault localization for functional failures is usually a very complex task, especially because a deep knowledge of all the functionalities of the device is often required. In addition, when the part is analyzed in application conditions, the interpretation of the anomalous emissions in the failed part and its link to the failing elementary component is not so obvious. The adoption of the analog quiescent current (IDDa) allows to address directly the failing elementary component inside the suspected block.

Viewing the cross section of wafers with glass carriers has always been a challenging task. Add on to observing and determining the glue coverage is an uphill struggle due to the fragile nature of the glue. The traditional technique of cleaving wafers equipped with glass carriers is neither promising nor highly successful. In addition to the mentioned disadvantages, the presence of glass carrier would mean cleaving the wafer with a diamond scriber, a dangerous technique due to the possibility of fragmentation of the glass carrier which could be a potential safety hazard. Time consuming, low success rate, lack of finesse and potential safety hazard of the conventional cleaving method had paved the path of an alternative technique to assess glue coverage for wafers equipped with glass carriers. This manuscript would give an elaborate insight of a novel technique employed in analysing the glue coverage of wafers with glass carriers.

Fault Injection Attacks (FIAs) have become prolific and effective methods of violating the integrity and confidentiality of integrated circuits and electronic systems. FIAs can be accomplished using clock-glitch, voltage glitch, laser, optical instruments, and electromagnetic (EM) emanation. One promising solution to detect FIAs is to use on-chip sensors to capture the attacks’ impact. However, the variety of FIAs has led to numerous custom-designed sensors for each of them, challenging the feasibility of the implementation and introducing a large overhead. This paper proposes developing a universal Fault-to-Time Converter (FTC) sensor that can effectively detect all the aforementioned FIAs while requiring minimal overhead. The FTC sensor converts the effects of faults injected by an FIA method into “time” that is measurable. Then, the “time” difference can be analyzed further to identify whether an attack has been carried out successfully. The sensor design can be easily implemented in both FPGA and ASIC platforms. Our FTC sensor implementation in FPGA platforms demonstrates that the design can effectively differentiate various FIA attack scenarios with its encoded output. The FTC sensor can also be extended to cover other fault attacks that have a similar impact on the victim device (i.e., affecting circuit timing).

Copper (Cu) material was extensively studied in the past years and widely implemented in high volume wire bonding process as a replacement of Gold (Au) material during semiconductor device fabrication. No doubt, Cu wire provide low cost alternative to gold with higher thermal and electrical conductivity, but it does pose some drawback especially after reliability stress. One of the most common problem was ball lifted after component gone through several reliability stress tests. In this paper, several FA analytical techniques and procedures will be discussed in detail to demonstrate the use of these techniques in ball lifting investigation.

This paper describes the new Cameca Akonis secondary ion mass spectrometry (SIMS) tool, which was developed to fill a critical gap in semiconductor fabrication processes by providing high throughput, high precision detection for implant profiles, composition analysis, and interfacial data directly in the semiconductor manufacturing line. The system enables automation in the primary ion column to ensure repeatability across tools for fabrication-level process control and tool-to-tool matching.

As the electronics industry moves towards miniaturization, the semiconductor industry provided packaging innovations to meet the demands for smaller footprints. One of the packaging solutions is the small outline transistor (SOT) which is widely used in various applications including automotive engine downsizing. Decapsulation of small packaged devices like a 1.3mm by 2.9mm SOT is one of the greatest challenges in failure analysis. The destructive nature of decapsulation may cause inadvertent and permanent damage, hindering further electrical verification on the unit. In this paper, a novel method for decapsulating SOT devices is presented utilizing the use of acrylic molding to avoid damage on the units during decapsulation process. Results show that the use of acrylic molding is an effective method in decapsulating SOT packaged devices maintaining die functionality, hence, addressing the decapsulation issues and risks caused by other existing decapsulation methods.

This paper presents conceptual application of AI in Failure Analysis to connect to various databases in semiconductor manufacturing and generating interactive data visualization to isolate root cause of failure faster vs traditional methods. Generally available low-cost software application like Microsoft Power BI (Business Intelligence) is utilized to visualize big data to isolate failure modes at wafer, die, and package level. This historic data visualization knowledge is further used by failure analyst to process failure mode isolation much faster based on failed package unit history. Semiconductor manufacturing companies have various big data such as wafer fab processing, die level test, or wafer sort and packaged die testing including customer return. MS Power BI application has ability to connect to these separate big databases and create unified data visualization to isolate failure modes through faster inter-connectivity and "connecting the dots" to provide bigger picture or drill down to finer unit level detail. This level of visualization utilizes already available info/data to help reduce overall time-to-defect. With this failure background, engineers can plan fault isolation and analysis and reduce overall time to find root-cause of failure.

There are many wafer level tests, such as Fail Bit Count (FBC), where conventional statistical analysis methods are inadequate because the associated data do not follow a normal distribution. This paper introduces a statistical failure analysis technique that does not rely on location and scale parameters and is thus able to handle such cases. It describes the math on which the method is based and explains how to determine effect size (ES) using the quantile comparison equivalence criteria (QCEC) and a statistical parameter, called the center of dispersion (CoD), that distinguishes between center difference and dispersion difference. It also includes a case study showing how the new method is used to assess the effect of a process change on dynamic random access memory test data and how it compares in terms of accuracy with conventional statistical techniques.

Planar deprocessing is a vital failure analysis technique for semiconductor devices. The basic concept is to expose an area of interest (AOI) by removing unnecessary material while maintaining planarity and surface evenness. Finger deprocessing is a widely used material removal technique, particularly for fin field-effect transistors (FinFETs). Here, success depends on certain factors, one of which is the location of the AOI. If the AOI is near the edge of the chip, finger deprocessing can be very difficult because material removal rates are much higher there than at the center of the chip. Plasma focused ion beam (PFIB) planar deprocessing is the preferred solution in such cases, but many labs cannot afford a PFIB system. To address this challenge, a sample preparation method has been developed that uses dummy chips to effectively eliminate edges. With dummy chips placed edge-to-edge with test chips, planar deprocessing can be achieved using conventional finger deprocessing techniques. This paper describes the newly developed method, step by step, and presents two examples demonstrating its use.