Logic State Imaging (LSI) using Infra-Red Emission Microscopy (IREM) [1-4] has been an indispensable technology for silicon CMOS process development and product debug applications. Its main limitations are relatively poor spatial resolution due to the broadband near-infrared photons emitted, and poor Signal to Noise Ratio (SNR) with low voltage and low leakage processes and products. Continuous-Wave Laser Scanning Microscope (CW-LSM) based Signal Imaging and Probing (CW-SIP) [5-9] technology is also widely used. It features inherently better spatial resolution than IREM, due to the use of monochromatic 1319nm or 1064nm laser light, and high SNR due to its weaker dependence on voltage and leakage, and, for signal imaging applications, the use of narrow band detection to reduce noise. However, CW-SIP can only detect modulating signals, so it couldn’t previously be applied to LSI. In this paper, we introduce an innovative approach that overcomes this limitation to enable Laser Logic State Imaging (LLSI). Actual fault isolation and design debug cases using this technology are presented to show its advantages in terms of resolution (>50% better), SNR (>2X better) and throughput time improvement, especially at low voltages (down to 500mV).

Laser-assisted device alteration (LADA) is an established technique used to identify critical speed paths in integrated circuit. In this paper, the characterization of continuous wave 1340nm laser induced currents and the LADA failure rate show that a two photon absorption explanation for the LADA effect is not plausible. The following sections confirm the results of a 28nm-node nMOS transistor using a 2.45NA solid immersion lens. The effects of global heating to that of local laser heating are then compared. The paper shows that the LADA response time to approximately 1300nm irradiation is << 100ns. It explains LADA at approximately 1300nm, free carrier absorption in the silicon and in the local silicide layers, and presents selected 1320nm LADA images on 28nm-node devices. Finally, it shows 1064nm LADA images on the same structure that indicate that 1064nm interaction with transistors is related to free carrier absorption, rather than electron-hole pair creation.

Laser-assisted device alteration (LADA) is an established technique used to identify critical speed paths in integrated circuits. LADA can reveal the physical location of a speed path, but not the timing of the speed path. This paper describes the root cause analysis benefits of 1064nm time resolved LADA (TR-LADA) with a picosecond laser. It shows several examples of how picosecond TR-LADA has complemented the existing fault isolation toolset and has allowed for quicker resolution of design and manufacturing issues. The paper explains how TR-LADA increases the LADA localization resolution by eliminating the well interaction, provides the timing of the event detected by LADA, indicates the propagation direction of the critical signals detected by LADA, allows the analyst to infer the logic values of the critical signals, and separates multiple interactions occurring at the same site for better understanding of the critical signals.

The application of lockin phase mapping of modulated reflectance with SIL is discussed in detail, particularly the socalled ghost mapping signal in STI neighboring to active regions. The different lockin phase between active regions and ghost regions showed clearly that both of them have different physical origins. The phase transition between active regions provides an enhancement of spatial resolution for defect localization in scan cell and sub blocks.c

Visible light laser voltage probing (LVP) for improved backside optical spatial resolution is demonstrated on ultra-thinned samples. A prototype system for data acquisition, a method to produce ultrathinned SOI samples, and LVP signal, imaging, and waveform acquisition are described on early and advanced SOI technology nodes. Spatial resolution and signal comparison with conventional, infrared LVP analysis is discussed.

By adding a transmission grating into the optical path of our photon emission system and after calibration, we have completed several failure analysis case studies. In some cases, additional information on the emission sites is provided, as well as understanding of the behavior of transistors that are associated to the fail site. The main application of the setup is used for finding and differentiating easily related emission spots without advance knowledge in light emission mechanisms in integrated circuits.

The Laser Voltage Imaging (LVI) technique, introduced in 2007 [1][2], has been demonstrated as a successful defect localization technique to address problems on advanced technologies. In this paper, several 28nm case studies are described on which the LVI technique and its derivatives provide a real added value to the defect localization part of the Failure Analysis flow. We will show that LVI images can be used as a great reference to improve the CAD alignment overlay accuracy which is critical for advanced technology debug. Then, we will introduce several case studies on 28nm technology on which Thermal Frequency Imaging (TFI) and Second Harmonic Detection (two LVI derivative techniques) allow efficient defect localization.

Fault localization on functional macros during advanced technology development requires a complex combination of tester based diagnostics and image based techniques including laser voltage imaging (LVI), laser voltage probing (LVP), critical parameter analysis (CPA) with laser stimulation and photon emission microscopy (PEM). These techniques are exemplified in the following three case studies. The first case involves a voltage sensitive SRAM block fail which was localized to a resistive via through the use of CPA, LVI and LVP. The second case demonstrates how a hard fail (a net-to-net metal short) in a scan chain was localized through use of tester based diagnostics, LVI, LVP and PEM. Finally, the last case shows how a condition sensitive failing latch chain was localized through CPA, LVI, LVP and PEM. Subsequent atomic force probing (AFP) identified source-drain leakage in one of the localized devices, and TEM analysis revealed a dislocation in the failing FET. Each of these cases demonstrates the value in utilizing tester based diagnostics along with laser based imaging and photon emission microscopy to localize failures.

Laser Voltage Imaging (LVI) has become a well-established method for isolating scan-shift (i.e., scan chain integrity) tests failures [1, 2]. When LVI is coupled with time-domain information acquired using Continuous-Wave Laser Voltage Probing (CW-LVP) [3], the Physical Failure Analysis (PFA) success rate exceeds 90% for all types of failing conditions, from hard stuck-at fails to soft transition fails. This combination of Electrical Failure Analysis (EFA) techniques is effective because of its ability to pre-isolate the defect to a small enough area for successful PFA. While high PFA success rates are proven, there remains the issue of throughput: CW-LVP can be time consuming, and techniques that minimize the need for it are important. This paper introduces a novel LVI methodology that incorporates phase information [4] and reduces the need for CW-LVP for certain types of failures. Case studies will be presented.

Recent developments and improvements of laser probing techniques are a good complement to traditional techniques like emission microscopy (static and dynamic) or laser stimulation (also static and dynamic, based on thermal or photoelectric stimulus) for the investigation of failure analysis and diagnostic of integrated circuits. Laser probing techniques have in fact evolved from mainly pulsed approach with high bandwidth [1] to other methodologies based on Continuous Wave (CW) [2,3,4,5]. The bandwidth of these CW approaches is generally lower than pulsed techniques and fine characterization of rising and falling edges or measurement of very small timing shifts can be more difficult or not possible for high speed devices. This bandwidth limitation is most of the time due to the amplification chain. But, CW probing bandwidth is good enough, and continuously improving, to identify directly or indirectly timing issues and to identify bad digital or analog behavior. The setup is also much easier than pulsed laser systems which require complicated synchronization between the system timebase and the device. On this other side new internal analysis modes have been introduced with for example some mapping mode based on frequency analysis or on timing degradation identification through second harmonic analysis [6,7]. At the same time these techniques have pushed the capabilities of a lot of existing tools to investigate low current, low voltage and/or low frequency devices such as analog parts, transmission gates and configurations when the defect cannot be activated at normal or high voltage. Comparison with EMission MIcroscopy (EMMI) in dynamic mode, which can have the higher bandwidth [8] is then possible.

We describe a test chip designed and fabricated in 32nm CMOS SOI. The test chip was developed to assist in the characterization and testing of hot electron emission based test systems for both existing and forthcoming technology nodes, and contains circuit structures of increasing density and complexity. We also describe some unique circuit functions that may be of use in other applications

In this paper, we discuss the use of a tester-based methodology to enhance the spatial resolvability and interpretation of time-integrated and time-resolved emission measurements. This technique, first presented at [1] for chip diagnostics and failure localization, is very powerful for extending the capability of modern analytical tools beyond the limits of existing optics and detectors. In particular, we will discuss how the proposed method works and present several test cases for both static and dynamic emission measurements that allow signals from gates 150 nm apart to be resolved.

Soft Defect Localization (SDL) is a laser scanning methodology that is commonly used to isolate integrated circuits soft defects. The device is exercised by a functional vector set in a loop manner while localized laser heating stimulates a change in the pass/ fail (P/F) response at the location of the defect or critical path. Although SDL is effective for this purpose, long scan time arising from test overheads, can be a concern to turnaround time for root cause understanding. In this paper, an optimized scheme on synchronous SDL that has a potential to eliminate more than 90% of tester overheads and improve overall SDL test time by at least 17% is proposed. This is achieved by optimizing SDL test loop algorithm.

Lock-in IR-OBIRCH analysis, as a kind of static thermal laser stimulation (S-TLS) technique, is very effective to isolate a fault for the parametric failure cases. However, its capability is limited to localize a defect when the IC is operated under a defined operating condition. Whereas the dynamic thermal laser stimulation (D-TLS) technique is good at locating a fault while the IC is operated under some functions to activate the failure. In this paper, a novel method is presented to realize DTLS just by Lock-in IR-OBIRCH assisted with a Current Detection Probe Head. Two cases are studied to demonstrate the effectiveness of this method.

Fault injection from infrared laser is a common practice among Information Technology Security Evaluation Facility (ITSEF) labs for testing CMOS circuits, and obtained effects are very versatile. However, from our point of view, the details of the phenomenona that occur in the integrated circuit have yet to be investigated. The common hypothesis is that the photoelectric current created during the light stimulation flows through the P-N junctions, and corrupts voltage outputs of the cells. In this paper, we consider the vertical parasitic bipolar junction transistors inherent to CMOS bulk devices. We show that these parasitic transistors contribute to the injected fault at a higher rate than just the P-N junctions of the OFF MOS side. There are two features of such results. First, the space charge region of the N-well / P-substrate junction is wide and will induce a stronger photocurrent. Second, this current will be amplified by the parasitic bipolar transistor and thus lead to more effects. These results are obtained by electrical simulations on a CMOS inverter. The size of the laser spot is taken into account via neighboring cells that are also illuminated. To induce an effect, small spot size needs a very high-power density, which is not always achievable. Increasing the illuminated area to inject more power is then a solution; simulations illustrate this point.

Microsystems-enabled photovoltaics (MEPVs) are microfabricated arrays of thin and efficient solar cells. The scaling effects enabled by this technique results in great potential to meet increasing demands for light-weight photovoltaic solutions with high power density. This paper covers failure analysis techniques used to support the development of MEPVs with a focus on the laser beam-based methods of LIVA, TIVA, OBIC, and SEI. Each FA technique is useful in different situations, and the examples in this paper show the relative advantages of each method for the failure analysis of MEPVs.

Differential thermal measurements have been extended beyond simple fault isolation to quasi and fully dynamic test conditions. A new technique of Dynamic Digital Modulation has been developed that allows highly sensitive differential thermal measurements during active device operations. A quadrature version of the modulation also produces a thermal time constant map that allows for direct visualization of heat flow within a device structure. A wide range of potential applications in failure analysis, reliability and reverse engineering are opened up. Examples include in situ identification of resistive bonds, internal heat flow in packaged devices and die, dynamic heat loading, and localization of structural elements for reverse engineering.

To improve the long-term stability of AlGaN/GaN HEMTs, the reduction of gate and drain leakage currents and electrical anomalies at pinch-off is required. As electron transport in these devices is both coupled with traps or surface states interactions and with polarization effects, the identification and localization of the preeminent leakage path is still challenging. This paper demonstrates that thermal laser stimulation (TLS) analysis (OBIRCh, TIVA, XIVA) performed on the die surface are efficient to localize leakage paths in GaN based HEMTs. The first part details specific parameters, such as laser scan speed, scan direction, wavelength, and laser power applied for leakage gate current paths identification. It compares results obtained with Visible_NIR electroluminescence analysis with the ones obtained by the TLS techniques on GaN HEMT structures. The second part describes some failure analysis case studies of AlGaN/GaN HEMT with field plate structure which were successful, thanks to the OBIRCh technique.

This paper presents two different case studies that highlight the use of reflected light imaging in laser scanning microscopy. In the first case study, the exact location of defects in metal comb test structures were much easier to detect with reflected light imaging than with thermally-induced voltage alteration (TIVA). This case study also shows visible-wavelength TIVA defect localization using a 532-nm laser. A comparison between 532-nm TIVA and conventional 1320-nm TIVA is made to show the resolution improvement with the visible laser. In the second case study, the cause of a linear string of bit failures was localized easily with backside reflected light imaging. It is observed that the indicated sites matched the light-induced voltage alteration signals and the failing cells in the bit map. In both of the case studies, the reflected light images have proved very helpful in the localization and characterization of failing devices or test structures.

This paper presents a case study on photon emission from metals and demonstrates the capability of Emission Microscopy Si-CCD camera to detect micro metal bridges on functional failures of Analog devices.