When considering CDM-like discharge, as it happens frequently in modern high-speed process and test equipment, it is important to avoid a so-called hard discharge in various electrostatic discharge (ESD)-sensitive devices. This study presents the results of experiments that were conducted to characterize the nature of hard discharge in various ESD sample materials: electrical pre-characterization, hard- vs. soft discharge test, oscilloscope measurements of the discharge characteristics, thickness measurements of metal table coatings and mates, and chargeability experiment. The results show that, following the existing standards in semiconductor manufacturing, hard CDM discharge cannot be prevented within the standardized lower resistance bandwidth. Insofar, the related standards ANSI 20.20 and IEC EN 61340-5-1 need to undergo a significant revision in the near future. For failure analysts, the results should be taken into consideration in order to advice useful corrective actions when accompanying client audits or doing ESD risk evaluations, especially within automated process equipment.

The limitations of Moore’s Law have led to alternatives in semiconductor packages that provide more functionality. Stacking multiple chips in 2.5D and 3D configurations has become a common solution. During the development of these technologies, test chains of chip to chip micro bumps and thru silicon via’s (TSV’s) at various regions within the stack are often employed. These present new challenges to the already difficult process of localizing open and resistive chain fails deep within the stack for root-cause analysis. A combination of quick and effective fault isolation techniques is often required to reliably isolate an open in a time critical situation. Capacitive measurements is a useful technique in some cases for obtaining a quick general location of an open. Magnetic Field Imaging (MFI), specifically Space Domain Reflectometry (SDR), is a non-destructive technique that can provide a relatively accurate location of an open. Electron Beam Absorbed Current (EBAC) is another useful technique in confirming and further isolating the open as the region of interest of the sample is approached via cross-sectioning or planar deprocessing. Case studies using these three techniques are presented and their strengths and weaknesses are discussed. The case studies focus on ìbump and chip bump chains in 2.5D samples.

New heterogeneous 3D integration schemes and continuing miniaturization of semiconductor packaging components, such as micropillars, are driving demand for substantive changes to conventional PFA (physical failure analysis). In particular, desired performance capabilities include the ability to nondestructively determine failures within seconds to minutes. New tools should be quantitative, have sufficient resolution to determine sub-micron sized defects and voids in TSVs at the wafer or package level. It should also measure thickness and their material composition of multilayer structures above the wafer surface, such as microbumps, or those below the surface including UBM and RDL. In this paper we are introducing a novel x-ray fluorescence microscope technique capable of solving the above applications in advanced packaging for PFA and process development. The same technique can also be applied in the front end metrology of new gate materials, 3D FinFET structures within test structures in patterned wafers. Characterization of sub nanoscopic changes (sensitivity of sub-angstrom) in film and dopants deposited in 3D structures will also be shown. With its high sensitivity for trace materials, contamination analysis of post hard mask residue, post metal etch residue especially in high aspect ratio structures is also possible.

Dissimilarities of thermal expansion coefficient between chip and package materials results in stress and strain at the solder interconnect leading to fatigue failures. Underfill is used between chip and package to reduce the interfacial stress and hence increase reliability. In this work, four flipchip package test vehicles underwent thermal cycling to accelerate the stress and were investigated systematically with different failure analysis techniques to study their failure modes. The prevalent failure mode was observed to be at the corner area between the chip and package using different advanced failure analysis techniques. This work demonstrates the technical complexity of analyzing stress induced defects and provides insight into CPI-based material selection.

Pure nickel lidded TO style packages are a common packaging type for active microelectronics with application in various fields including commercial, aerospace and defense. This paper will focus on the history of nickel flakes in the industry, current trends and failure analysis findings, and future considerations for this potential failure mechanism. In 2004 Hi-Rel Laboratories became involved in an important nickel flake study which led to further inspections to document and evaluate nickel flakes in TO style lids from various customers and manufacturers. Through 2015 these inspections also assisted manufacturers to evaluate the effectiveness of their lid preparation and various cleaning methods for this package style, resulting in a substantial reduction in total number of nickel flakes greater than the specified critical dimension. In 2019 investigations were rekindled after the discovery of a suspected nickel flake-induced failure in transistors from a manufacturer not involved in prior analyses. As part of the investigation, which included nickel flake inspection of 38 total transistors from 1992, 2010, 2011 and 2017 lot date codes, the components were subjected to various environmental conditions including vibration, mechanical shock, mild thermal cycling, ionized airflow and degaussing. It was discovered that degaussing alone greatly affected the adhesion of the nickel flakes to the internal surfaces, causing the majority of the flakes to break free. The methodology, findings and implications of this analysis will be discussed.

This paper describes the investigation of donut-shaped probe marker discolorations found on Al bondpads. Based on SEM/EDS, TEM/EELS, and Auger analysis, the corrosion product is a combination of aluminum, fluorine, and oxygen, implying that the discolorations are due to the presence of fluorine. Highly accelerated stress tests simulating one year of storage in air resulted in no new or worsening discolorations in the affected chips. In order to identify the exact cause of the fluorine-induced corrosion, the authors developed an automated inspection system that scans an entire wafer, recording and quantifying image contrast and brightness variations associated with discolorations. Dark field TEM images reveal thickness variations of up to 5 nm in the corrosion film, and EELS line scan data show the corresponding compositional distributions. The findings indicate that fluorine-containing gases used in upstream processes leave residues behind that are driven in to the Al bondpads by probe-tip forces and activated by the electric field generated during CP testing. The knowledge acquired has proven helpful in managing the problem.

An effective method is presented to locate certain failure sites on exposed junction of insulated-gate bipolar transistor (IGBT) devices. High emitter to collector leakage current, hereafter called ICESR, is an IGBT failure mode. The leakage current is typically related to the exposed P+/N+ junction on the die sidewall. Solder die attach residue bridging or silicon damage at this exposed P+/N+ junction are common causes of ICESR leakage. The die attach residue can be dislodged during decapsulation resulting in loss of failure information. A failure analysis flow will be described to precisely locate the ICESR leakage site without disturbing any possible die attach residue.

An effective method is presented to locate certain failure sites on exposed junction of insulated-gate bipolar transistor (IGBT) devices. High emitter to collector leakage current, hereafter called ICESR, is an IGBT failure mode. The leakage current is typically related to the exposed P+/N+ junction on the die sidewall. Solder die attach residue bridging or silicon damage at this exposed P+/N+ junction are common causes of ICESR leakage. The die attach residue can be dislodged during decapsulation resulting in loss of failure information. A failure analysis flow will be described to precisely locate the ICESR leakage site without disturbing any possible die attach residue.

Advanced package technology often includes multi-chips in one package to accommodate the technology demand on size & functionality. Die tilting leads to poor device performance for all kinds of multi-chip packages such as chip by chip (CbC), chip on chip (CoC), and the package with both CbC and CoC. Traditional die tilting measured by optical microscopy and scanning electron microscopy has capability issue due to wave or electron beam blocking at area of interest by electronic components nearby. In this paper, the feasibility of using profilemeter to investigate die tilting in single and multi-chips is demonstrated. Our results validate that the profilemeter is the most profound metrology for die tilting analysis especially on multi-chip packages, and can achieve an accuracy of <2μm comparable to SEM.

In multilevel 3D integrated packaging, three major microstructures are viable due to the application of low volume of solders in different sizes, and/or processing conditions. Thermodynamics and kinetics of binary compounds in Cu/Sn/Cu low volume interconnection is taken into account. We show that current crowding effects can induce a driving force to cause excess vacancies saturate and ultimately cluster in the form of microvoids. A kinetic analysis is performed for electromigration mediated intermetallic growth using multiphase- field approach. Faster growth of intermetallic compounds (IMCs) in anode layer in the expense of shrinkage of cathode IMC layer in shown. This work paves the road for computationally study the ductile failure due to formation of microvoids in low volume solder interconnects in 3DICs.

This paper describes a method for obtaining high-resolution ultrasonic inspection images of semiconductor packages. We evaluated the effect of the incident ultrasonic frequency on the resolution and defect detection. When the incident frequency of the ultrasonic transducers is changed from 300 MHz to 400 MHz, the capability to detect package defect improves from 2.5 µm to 1.0 µm. The observed images of semiconductor packages proves that a 400 MHz transducer can be applied to inspect sophisticated LSIs.

Innovative in situ X-ray metrologies for package failure analysis (FA) were developed to understand solder thermal interface materials (STIM) package process and failure mechanisms through elevated temperature. Dynamic STIM void formation mechanism and STIM bleeding-out dependency on reflow were observed. It was found that long sit time before STIM liquidus temperature helps to minimize the STIM void formation and fast cooling mitigates the STIM bleed-out risk. Our studies demonstrate that in situ metrologies offer direct guidance to packaging process optimization and accelerate root-cause identification for temperature induced package failures; therefore, it improves throughput-time for packaging technology development.

With the growing complexity and interconnect density of modern semiconductor packages, package level FA is also facing new challenges and requirements. 3D X-Ray Microscopy (XRM) is considered a key method to fulfill these requirements and enable high success FA yield. After a short introduction into the basic principles of lab-based X-Ray tomography, 2 different approaches of X-Ray investigations are discussed and an integration into the daily FA flow is proposed. In the first example, fault isolation on a fully packaged device is demonstrated using a stacked die device. In the second example, a newly developed sample preparation flow in combination with Nanoscale 3D X-Ray Microscopy for Chip-Package-Interaction and Back-end-of-line feature imaging is introduced.

Magnetic field imaging is a well-known technique which gives the possibility to study the internal activity of electronic components in a contactless and non-invasive way. Additional data processing can convert the magnetic field image into a current path and give the possibility to identify current flow anomalies in electronic devices. This technique can be applied at board level or device level and is particularly suitable for the failure analysis of complex packages (stacked device & 3D packaging). This approach can be combined with thermal imaging, X-ray observation and other failure analysis tool. This paper will present two different techniques which give the possibility to measure the magnetic field in two dimensions over an active device. Same device and same level of current is used for the two techniques to give the possibility to compare the performance.

The given project is to benchmark typical preparation methods under the aspect of the influence of initial intrinsic stresses inside electric components. Raman spectroscopy has been applied as well as the piezo resistive readout on a specifically designed model stress monitoring chip.

As various types of DRAM package have been developed, new defects in interconnection in chip have been discovered after assembly process such as flip chip bump mount or wire bonding. There are lots of regular inspections in manufacturing process to detect assembly defects, but it is not easy to find all of the defects. We used a method to classify physical failures based on electrical measurements. Conventional open and short tests by using ISVM were used to support the mass production. External voltage sweep is employed to distinguish weak defects from strong defects of interconnection. Finally, a proposed method was verified with statistical analysis of 800,000 FBGA DRAM chips and physical analysis of failure chips.

Cu wires were bonded to AlSi (1%) pads, subsequently encapsulated and subjected to uHAST (un-biased Highly Accelerated Stress Test, 130 °C and 85% relative humidity). After the test, a pair of bonding interfaces associated with a failing contact resistance and a passing contact resistance were analyzed and compared, with transmission electron microscopy (TEM), electron diffraction, and energy-dispersive spectroscopy (EDS). The data suggested the corrosion rates were higher for the more Cu-rich Cu-Al intermetallics (IMC) in the failing sample. The corrosion was investigated with factors including electromotive force (EMF), self-passivation of Al, thickness and homogeneity of the Al-oxide on the IMC, ratio of the Cu-to-Al surface areas exposed to the electrolyte for an IMC taken into account. The preferential corrosion observed for the Cu-rich IMC is attributed to the high ratios of the surface areas of the cathode and anode that were exposed to the electrolyte, and the passivation oxide of Al with the lower homogeneity. The corrosion of the Cu-Al IMC is just a manifestation of the well-known phenomenon of dealloying. With the understanding of the corrosion mechanisms, prohibiting the formation of Cu-rich IMCs is expected be an approach to improve the corrosion resistance of the wire bonding.

The Aerospace and Defense (A&D) markets are starting to use plastic packages more significantly for Space and Military ruggedized applications. But plastic packages are also inherently less reliable than ceramic devices for A&D applications. The key to the successful use of plastic devices in A&D application is to qualify the devices for the intended application using industry accepted plastic encapsulated microcircuit (PEM) qualification techniques. This paper briefly recaps the test techniques known to be effective in assessing plastic part reliability. But more importantly, it presents actual PEM qualification data gathered over the last 15 years involving over 400 individual PEM Qual lots. The paper also shows the failures modes associated with plastic packages and Cu bond wires. SEM, X-Ray, and Acoustic Microscope images were obtained for the failure modes associated with plastic packages and Cu bond wire.

Advances in electronic packaging are fueled by the insatiable appetite that consumers have for bandwidth in mobile appliances. The technological answer to this demand is increase the interconnect count and shrink the pitch, solder volume and height. The features of interest and the defects in these packages are becoming increasingly smaller. Consequently, the characterization of these defects becomes more challenging due to the smaller size and new material structures. New package structures must pass the JEDEC standard tests and a critical part of qualifying new packages as products is proper identification of the root cause of failures. Therefore, innovative solutions to correct the fundamental problems in the development process enable new package solutions to be brought to the market. In this paper we describe an alternative failure analysis workflow involving X-ray microscopy which offers several advantages over standard imaging techniques. The nondestructive nature of x-ray microscopy enables engineers to image parts throughout the entire environmental stress cycle for more accurate determination of the root cause of failures. Additionally, a larger number of interconnects may be sampled, defect isolation in z direction for stacked die packages is made easier and subsequent imaging techniques may be used to complement the data. Both 3 dimensional images of defects as well as 2 dimensional cross sections will be shown to effectively analyze the true root cause of failures.

Decap methods which have been used for copper wire packages are not effective for silver wire packages, and the authors recognized the need for the development of a novel method. This paper discusses the development of various processes to decap silver wire packages with acid. The first decap method developed for a silver wire package was to add hydrochloric acid to fuming nitric acid. This method proved insufficient to prevent silver wire from dissolving when solution temperature is 60 degree. The authors then developed the Saturation Etch method for decapsulating silver wire packages using a chemical solution. When dissolution amount of silver wire put in normal fuming HNO3 is defined as 100%, the authors were able to achieve its reduction to less than 3% by using saturated acid. This method is also effective for copper wire packages, and damages to wires can be minimized by dissolving copper into acid.