In the current generations of devices the die and its package are closely integrated to achieve desired performance and form factor. As a result, localization of continuity failures to either the die or the package is a challenging step in failure analysis of such devices. Time Domain Reflectometry [1] (TDR) is used to localize continuity failures. However the accuracy of measurement with TDR is inadequate for effective localization of the failsite. Additionally, this technique does not provide direct 3-Dimenstional information about the location of the defect. Super-conducting Quantum Interference Device (SQUID) Microscope is useful in localizing shorts in packages [2]. SQUID microscope can localize defects to within 5um in the X and Y directions and 35um in the Z direction. This accuracy is valuable in precise localization of the failsite within the die, package or the interfacial region in flipchip assemblies.

Scanning superconducting quantum interference device (SQUID) microscopy using high-TC SQUID sensor has been slowly gaining acceptance in the failure analysis (FA) community as a number of silicon device manufacturers are applying the tool and technique to an ever-broadening spectrum of silicon technologies for detecting the location of leakage and short failures by imaging the current path through the die and package. This paper will present the application of scanning SQUID microscopy to short isolation on die and explore the integration of this technique into the FA flow. From the examples presented in this paper, it can be seen that die level short isolation has been possible even when the separation from SQUID sensor to current is about 800-900µm. Several potentially useful techniques that will increase the accuracy of locating the die level short nondestructively are also discussed.

We evaluated laser ablation and sandblasting as preparation methods for package related failures and for backside analysis of ICs. With laser ablation we uncovered gold wedges on an internal board of a PLFBGA package without damage of the gold wires and the board metallization. This was possible by optimization of the laser pulse energy and the pulse repetition rate and by limitation of the ablation area. Sandblasting showed to be a gentle way for backside thinning down to 60 μm silicon thickness. For a surface smoothness sufficient for IR imaging a subsequent planarization treatment is necessary.

Time Domain Reflectrometry or TDR is an analytical technique used to determine the impedance and electrical length of conductors. This relatively inexpensive technique utilizes a pulse card and digital oscilloscope whereby the reflected signal amplitude from an initiating pulse is measured versus time. The technique is useful for characterizing the impedance of a conductor in the time domain, and has traditionally been employed in board level analysis. More recently, TDR has been shown to be useful in electrically isolating integrated circuit package failures [1]. Historically, open failures on non-flip chip devices were resolved through relatively straight-forward, low risk methods in a failure analysis lab. Typically, root cause analysis involved simple verification on a curve tracer, non-destructive inspection using X-Ray imaging, chemical, thermal or mechanical decapsulation, optical and electron microscopy and as necessary, the use of mechanical probe isolation. The implementation of advanced flip chip package technology rendered the traditional isolation methodologies inadequate. After verification and X-ray inspection, a decision had to be made prior to subsequent destructive physical analysis as to the most probable failure location. Since the board interconnects, board interposer, and bump locations were not geometrically aligned, isolation of opens through physical cross-sectioning became risky, tedious and lengthy. These constraints were overcome through the use of TDR analysis. The authors have successfully incorporated the TDR technique into AMD’s microprocessor failure analysis flow, improving success rate, reducing risk and decreasing turn-around time. The paper will include a brief description of TDR theory and hardware, technical barriers that the authors encountered during implementation, sample preparation as well as details where the technique was successfully employed in failure isolation. The remaining portion of this paper provides illustrative examples where TDR was effectively utilized in the analysis of slot A cards, ceramic flip chip PGA pins, and internal package trace failures.

The focus of this article is on locating signal-to-ground shorts and plane-to-plane shorts using the time domain reflectometry (TDR) based fault isolation system. The article proposes two comparative techniques for plane-to-plane short location, both based on the secondary information in the TDR data. The first technique looks for the difference in secondary reflections in the TDR waveform and the second looks at the inductance of the current return path, which can be computed in IConnect TDR software. The article presents simple test board example for plane-to-plane short failure location and discusses the results obtained by applying the TDR technique to the measurements of a sample package under test. Locating a signal-to-ground short has been shown to present little difficulty over a comparable open fault locating task. However, with the true impedance profile and planar inductance analyses, the claim of impossibility of locating a plane-to-plane is effectively challenged in this paper.

A laser spallation technique to measure the tensile strength of thin film interfaces is introduced. In this technique, a laser-generated stress wave of nanosecond duration in the substrate spalls off (completely removes) a coating deposited on the substrate’s front surface. The threshold laser energy is converted into the tensile stress (strength) at the failure site (usually the interface) by using an optical interferometer. Because of the ultra-short duration of the stress wave loading, all plastic deformation processes that usually accompany the coating decohesion event are suppressed such that the measured value can be regarded as fundamental or intrinsic to the material system (including the defects, if any). Application of this technique to test planar as well geometrically heterogeneous interfaces in IC’s, substrates, and packages is demonstrated. The technique is used to quantify the degrading effects of moisture and in-situ temperature rise on the tensile strength of a polyimide/Si3N4/Si interface system whose strength was systematically degraded by exposing the samples to controlled humidity (50-70% RH) conditions for varying duration (12-96 hrs) and temperatures (30°C-150°C). These measurements of strength degradation can now be used to predict device reliability from a fundamental standpoint in conjunction with simulations capable of predicting time-dependent stress concentrations, moisture accumulation, and temperature rise at critical interfaces during processing and service environment in actual systems.

Bond pad characterization is usually performed by mechanical cross-sectioning as well as pull and shear tests. However, since all these methods apply mechanical forces to the bond pad, artifacts may result. Focused Ion Beam (FIB) characterization is a mechanically stress-free characterization method, which allows more accurate conclusions regarding the intermetallic behaviour of the bonding area. Some new approaches presented here show how to improve the FIB characterization procedure and to combine it with classical characterization methods.

This paper describes a new diagnostic technique for analyzing microstructural changes occurring to flip chip joints after accelerated thermal tests. Flip chip reliability was assessed at high temperatures, with and without the application of electrical bias. A combination of standard metallurgical polishing techniques and the use of a focused ion beam (FIB) lift out technique was employed to make site-specific samples for transmission electron microscopy (TEM) cross-sections. We studied evaporated 95Pb/5Sn bumps, on sputtered Cr/CrCu/Cu/Au as the under bump metallization (UBM). Thermally stressed samples were tested for electrical continuity and evaluated using 50 MHz C-mode scanning acoustic microscopy (C-SAM). Failed samples were crosssectioned and large voids at the UBM were observed optically. TEM specimens taken from the predefined UBM region of degraded flip chip devices provided critical microstructural information, which led to a better understanding of a cause of degradation occurring in the flip chip joints.

Next generation assembly/package development challenges are primarily increased interconnect complexity and density with ever shorter development time. The results of this trend present some distinct challenges for the analytical tools/techniques to support this technical roadmap. The key challenge in the analytical tools/techniques is the development of non-destructive imaging for improved time to information. This paper will present the key drivers for the non-destructive imaging, results of literature search and evaluation of key analytical techniques currently available. Based on these studies requirements of a 3D imaging capability will be discussed. Critical breakthroughs required for development of such a capability are also summarized.

The visual nature of Time Domain Reflectometry (TDR) makes it a very natural technology that can assist with fault location in BGA packages, which typically have complex interweaving layouts that make standard failure analysis techniques, such as acoustic imaging and X-ray, less effective and more difficult to utilize. This article discusses the use of TDR for package failure analysis work. It analyzes in detail the TDR impedance deconvolution algorithm as applicable to electronic packaging fault location work, focusing on the opportunities that impedance deconvolution and the resulting true impedance profile opens up for such work. The article examines the TDR measurement accuracy and the comparative package failure analysis, and presents three main considerations for package failure analysis. It also touches upon the goal and the task of the failure analysts and TDR's specific signatures for the open and short connections.

Detecting failure in electrical connectivity at the component packaging level is a major expenditure of the industry’s failure analysis (FA) resources. These package failures can result from material/manufacturing excursions, stress tests, and/or customer returns. However, many of the methods employed currently (such as X-ray or crosssectioning) can fall short in terms of throughput time, or success rate. Moreover, many FA techniques can be destructive and therefore leave the sample useless for subsequent tests. On the other hand, time domain reflectometry (TDR) can be used as a component packaging level FA tool which meets the needs of quickly, precisely, and non-destructively locating electrical connectivity problems in signal traces. Once the failure location has been pin pointed, other FA methods (X-ray, cross-section, etc.) can be used more easily to determine why the failure occurred. Since TDR testing involves no physical preparation, the sample will be completely intact for subsequent tests. TDR uses a low voltage, low current, and very short rise time voltage pulse to determine the impedance of a signal trace as a function of time. With a waveform of trace impedance versus time, not only can the presence of a failure be detected, but the distance along the trace to the anomaly can also be quickly determined. This paper presents TDR as a useful tool for package level failure analysis labs. The paper proposes one set of solutions for enabling effective TDR analysis (e.g., TDR test fixturing), and discusses some TDR methodologies for detecting and locating anomalies. The methodologies will be illustrated using three example cases that reflect some commonly used packaging technologies: Flip-Chip Organic Land Grid Array (FC-OLGA), Flip-Chip Pin Grid Array (FC-PGA), and Plastic Land Grid Array (PLGA).

The quality of the die attach is crucial for almost all power devices, as in most cases thermal and electrical transport is vertical through the die and its backside. For glue inspection, C-SAM through the lead frame is widely used. Ordinarily, one of the three following states of delamination is found: (A) no delamination, (B) delamination at the die, or (C) delamination at the lead frame. A general rule for the assignment of the brightness in C-SAM amplitude images to these states of delamination cannot be given. This is evidenced by contrast inversions observed with frequency variation of the applied ultrasound or variation of the glue thickness. Contrast inversions at images through the lead frame occur between areas of states (A) and (B). The calculation of ultrasonic echoes for a three-layer model (copper, glue, silicon) shows that the contrast inversions are connected to the first resonance of the glue in state (B). Here complicated shapes of the echoes are found in experiments and calculations, which helps to correctly assign brightness levels to delamination states. Additionally a flow for reliable glue investigation with the use of through-transmission SAM inspection is proposed.

Ever since the invention of the scanning acoustic microscope (SAM), a key objective has been the enhancement of the resolution in an interior image. Thus, an acoustic lens that can form an interior image with a shear wave has been designed. The use of this lens gives benefits such as an increase of lateral resolution in the interior image, a reduction in background noise caused by surface roughness, and a reduction of spherical aberration. Significantly, with the current trend towards microminiaturization of microelectronic packages, acoustic microscopy with higher resolution and removal of surface roughness can play an important role in diagnostic examinations and failure analysis. In this paper, applications for the lens in microelectronic IC packages will be summarized.

Stacked-chip scale package (S-CSP) is a new packaging technology introduced in the memory components market to effect chip miniaturization, a challenging trend in semiconductor assembly. The package is built by molding two stacked dice (Flash and SRAM) on bismaleimide triazine (BT) substrate. As this novel packaging technology offers solution to the challenge, it also poses complexity in the field of failure analysis in cases that the bottom die is the interest. Deprocessing these stacked dice while maintaining the functionality of the bottom die will be explained in detail. Prior the conduct of failure analysis (FA) and fault isolation (FI), deprocessing the failing unit containing only one die normally consists of chemical decapsulation. S-CSP sample preparation also adheres to this treatment in case the top die is the aim for analysis. On the other hand, if the concern shifts to the bottom die, sequential techniques involving precision polishing to die-to-die adhesive layer, chemical etching of adhesive and residual molding compound, and rebonding the bottom die on ceramic interposer, are employed. With the rebonded S-CSP bottom die, fault isolation could be performed further. This paper will also feature the mechanism behind the blown-up failure, a power test failure in memory devices, encountered during the package development when two types of die-to-die adhesives were selected and used. Consistent with the results of electrical characterization suggesting that S-CSP bottom die as the failing die, passivation damage is uncovered on the bottom die upon separation of the stacked dice. Material comparison points out that the hard, angular glass fillers of the die-to-die adhesive induce the damage. Polymer-filled adhesive performs better than the glass-filled adhesive as indicated by the results of the package characterization. Generally, this case exemplifies a packaging material-related failure. Moreover, the paper could serve as a reference material in the event that feasibility of packaging non-memory components in S-CSP is to be evaluated. The developed methodology of recovering the S-CSP bottom die would be a keystone in proacting for its FA readiness.

Delamination of mold compound from top-of-die surfaces in plastic encapsulated microcircuits (PEMs) can alter overall package stresses and cause wire bond or other types of mechanical failure. Liquid water may collect in these delaminated regions and cause metal corrosion. Exceedingly small quantities, even fractions of a monolayer, of adsorbed contamination on die may hinder intimate adhesion of the mold compound to the die surface and cause plastic to delaminate. This paper discusses the consequences of top-of-die delamination (TODD), surface contamination derived from wafer tape mounting that can cause it, and cleaning chemistry to remove surface contaminants in order to minimize it.

Surface Mount Technology (SMT) ceramic capacitors are widely used on virtually every type of electronic product. In computer systems, SMT capacitors populate the majority of electronic parts found on each Printed Circuit Assembly (PCA) within the product, primarily as bypass or coupling devices between power and ground. As such, the opportunity for failure is substantially higher than with other commonly used active or passive components. Additionally, the relatively small ceramic bodies are prone to mechanical damage. Their proportionately high numbers, sensitivity to mechanical stress and difficulty in isolating to a specific failing device on the PCA (since many of these parts are in parallel with many other identical capacitors) all combine to make the successful isolation and analysis of the root cause of failure particularly difficult for the failure analyst. Often, the cause of failure is misdiagnosed, or the evidence is compromised by the methods used to perform the analysis. This paper will discuss the common failure mechanisms associated with SMT ceramic capacitors, as well as some innovative non-destructive isolation tools and techniques, including C-Mode Scanning Acoustic Microscopy (C-SAM), Infrared thermography (IR) and Micro-Focus X-ray analysis. Several case studies will be cited which demonstrate each of the mechanisms and methods. Additionally, the processes used to properly analyze these defects will be examined.

A common pad finish on area array (BGA or CSP) packages and printed wiring board (PWB) substrates is Ni/Au, using either electrolytic or electroless deposition processes. Although both Ni/Au processes provide flat, solderable surface finishes, there are an increasing number of applications of the electroless nickel/immersion gold (ENi/IAu) surface finish in response to requirements for increased density and electrical performance. This increasing usage continues despite mounting evidence that Ni/Au causes or contributes to catastrophic, brittle, interfacial solder joint fractures. These brittle, interfacial fractures occur early in service or can be generated under a variety of laboratory testing conditions including thermal cycling (premature failures), isothermal aging (high temperature storage), and mechanical testing. There are major initiatives by electronics industry consortia as well as research by individual companies to eliminate these fracture phenomena. Despite these efforts, interfacial fractures associated with Ni/Au surface finishes continue to be reported and specific failure mechanisms and root cause of these failures remains under investigation. Failure analysis techniques and methodologies are crucial to advancing the understanding of these phenomena. In this study, the scope of the fracture problem is illustrated using three failure analysis case studies of brittle interfacial fractures in area array solder interconnects. Two distinct failure modes are associated with Ni/Au surface finishes. In both modes, the fracture surfaces appear to be relatively flat with little evidence of plastic deformation. Detailed metallography, scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), and an understanding of the metallurgy of the soldering reaction are required to avoid misinterpreting the failure modes.

In the never ending battle for smaller, faster, cheaper semiconductors, ESD protection is more and more becoming a driving factor. Since scaling the ESD protection devices usually means scaling the level of protection as well, methods for providing good ESD robustness in less real estate are required. By placing some ESD circuitry under the bond pads and maintaining good control over the wire bond process, good ESD levels can be obtained, excellent reliability can be achieved and significant die area can be saved.

Most semiconductor devices are sealed in plastic. Virtually all plastic encapsulated microcircuits (PEMs) look alike. The particular electronic molding compound (EMC) used to encapsulate a device cannot be known except from production records or firsthand knowledge of people familiar with the device. For a variety of reasons, an EMC may need to be explicitly identified. Pyrolysis of the EMC, followed by Fourier Transform Infrared (FT-IR) chemical analysis of the condensates of organic substances evolved by the pyrolysis, and comparison of the spectra with a reference library of known EMCs, provides a rapid means of specific EMC identification.

Ball shear forces of plastic ball grid array (PBGA) packages are found to decrease after reliability test. Packages with different ball pad metallurgy form different intermetallic compounds (IMC) thus ball shear forces and failure modes are different. The characteristic and dynamic process of IMC formed are decided by ball pad metallurgy which includes Ni barrier layer and Au layer thickness. Solder ball composition also affects IMC formation dynamic process. There is basically no difference in ball shear force and failure mode for packages with different under ball pad metallurgy before reliability test. However shear force decreased and failure mode changed after reliability test, especially when packages exposed to high temperature. Major difference in ball shear force and failure mode was found for ball pad metallurgy of Ni barrier layer including Ni-P, pure Ni and Ni-Co. Solder ball composition was found to affect the IMC formation rate.