The corrosion phenomenon was found at the edge area of bond pad under OM images after dicing saw. Experiment showed that the corrosion was related with the feed speed of dicing saw. From SEM and OM results, there were some abnormal contaminations around the corrosive area. Auger and TEM with EDX system were used to characterize the corrosive region and the related Al pad corrosion mechanism was discussed. In this paper, Cu rich and O rich layers were identified by TEM and EDX, which could be induced by galvanic cell reaction.

As the number of dice stacked within a microelectronic package increases, the need to maintain die surface integrity also increases. In this paper, one assembly packaging-related rootcause mechanism about passivation-metal damage (PMD) will be featured. The profile of inter-die adhesive was found to play an important role to maintain the integrity of die surface as more dice are stacked in a microelectronic package. Recommended solution to prevent this type of failure will be discussed.

During package qualification, a 5-die-stacked chip scale package was being marginally triggered on high stand-by current collectively known as Power ICCS failure. Affected lots are subjected to 3x reflow at 240°C. Post reflow failures include blown_up, high standby current in Vcc pin (ISBLO), and high standby current in Vccq pin (ISBLOQ). Backside chip-outs are observed on Die 1 and Die 3 of the three failures. Electrical validation showed that only Die 3 is failing. Corner crack on Die 3 is common to the blown_up and ISBLO failing units while crack on Die 3 backside is observed to propagate toward the active area on ISBLOQ failing units. Fracture analysis results show that the crack of the three failures all originated from die backside chip-out. Thermo-mechanical model of the package shows that, by design, Die 3 generates the highest stress concentration. Results show that if chip-outs are present on the area of the die with the highest stress concentration and the unit is subjected to reflow temperature of 240°C, die crack will propagate from the chip-out. This paper presents the unique failure mechanism observed on a 5-die-stacked chip scale package and the corrective actions applied to solve the issue.

Temperature humidity bias (THB) test is widely used to evaluate the moisture resistance of non-hermetic packages in semiconductor industry. During THB test, one kind of 90FBGA was found severely burned and the evidence has been completely destroyed. This brings a great challenge to failure analysis. In this paper, a double daisy chain structure substrate was designed to reproduce the short and burn failure. The substrate layout design, bias and high humidity environment were proved to be the three key factors inducing dendrite growth and burn failure. A “corner-missing” phenomenon inspected through nano-focus X-ray was reported and it could finally verify the theory of electrochemical migration. The countermeasure to prevent burn failure was proposed to the designers. The insulation property degradation due to THB test was evaluated.

Packages with the Modified Daisy-chain (MDC) die have been used increasingly to accelerate reliability stress testing of IC packaging during package development, qualification, and evaluation and reliability monitor programs [1]. Utilizing this approach in essence eliminates chip circuit failure mechanisms. Unlike packages with active die, in packages with the MDC die, when short occurred between two daisy-chain pairs of I/Os, there are four possibilities that can attribute to each pin of the two daisy-chain pairs. That makes the isolation of short failure difficult. Time Domain Reflectometry (TDR) is a well-described technique to characterize package discontinuity (open or short failure). By using a bare package substrate and a reference device, an analyst can characterize the discontinuity and localize it: within the package, the die-package interconnects, or on the die [2]. Scanning SQUID (Superconducting Quantum Interference Device) Microscopy, known as SSM, is a non-destructive technique that detects magnetic fields generated by current. The magnetic field, when converted to current density via Fast Fourier Transform (FFT), is particularly useful to detect shorts and high resistance (HR) defects [3]. In this paper, a new methodology that combines Resistance Analysis, TDR Isolation and SSM Identification for electrical debugging short in packages with the MDC die will be presented. Case studies will also be discussed.

Galvanic corrosion (two metal corrosion) on microchip Al bondpads may result in discolored or non-stick bondpad problem. In this paper, a galvanic corrosion case at bondpad edge will be presented. Besides galvanic corrosion (Al-Cu cell), a concept of galvanic corrosion (Al-Ti cell) is proposed, which is used to explain galvanic corrosion at bondpad edge with layers of TiN/Ti/Al metallization structure. A theoretical model of galvanic corrosion (Al-Ti cell) is proposed to explain chemically & physically failure mechanism of galvanic corrosion at bondpad edge. According to the theoretical model proposed in this paper, galvanic corrosion on microchip Al bondpads could be identified into two corrosion models: galvanic corrosion (Al-Cu cell) occurred mostly at the bondpad center and galvanic corrosion (Al-Ti cell) occurred specially at bondpad edge with TiN/Ti/Al metallization structure. In this paper, a theoretical model of galvanic corrosion (Ai-Ti cell) will be detail discussed so as to fully understand failure mechanism of galvanic corrosion the bondpad edge. Moreover possible solutions to eliminate galvanic corrosion (Al-Ti cell) are also discussed.

The need to miniaturize in the electronics industry is driving smaller form factors, and resulting in complex packaging innovations such as structures with multiple devices stacked inside a three dimensional package. These structures present a challenge for non-destructive fault isolation. Two such modules recently exhibited failures on the NASA Goddard Space Flight Center Solar Dynamic Observatory (SDO) during board-level testing. Each module consisted of eight vertically-stacked mini-boards, each mini-board with a single EEPROM microcircuit and capacitor, and connected by external gold metallization to module pins. Both failed modules exhibited low-resistance shorts between multiple pins. The orthogonal structure of the module prompted the use of magnetic current imaging (MCI) in three planes in order to construct an internal three-dimensional current path for each of the failed modules. Magnetic current imaging is able to “look through” non-magnetic, or de-gaussed packaging materials, allowing global imaging without physical deprocessing of the stacked EEPROM modules, in order to construct the internal current path and localize defects. To our knowledge, this is the first time that this has been done. Following global isolation of the defects, two types of magnetic sensors were used in parallel with limited deprocessing in order to more precisely characterize suspect failure locations before actually physically exposing the defects. This paper will show the process for using magnetic current imaging with both SQUID and magnetoresistive (GMR) sensors to isolate defects in two stacked EEPROM packages along with the final physical analysis of the defects. The failure analysis found that these devices were damaged by external heat, possibly during oven pre-conditioning or hot air soldering onto the board. The manufacturer, 3-D Plus, was not implicated in the failure.

Bond-pad integrity directly affects the performance of microelectronic devices. Bond-pad cracking and the related sub-pad cracking of Inter-Metal Dielectric (IMD) may introduce a high reliability risk and cause units to fail at environmental stress. Bond-pad cracks may be initiated by probing during wafer sort and the wire bonding process during assembly. This paper presents a comparative analysis of the various chemistries used for exposure and decoration of pad cracks. The investigation showed that a tri-iodine etch provides clean and artifact-free exposure of the TiN barrier layer of the pad and is the best (of the methods tried herein) for pad crack observation.

This paper presents a new fail mechanism for laser-marking induced die damage. Discovered during package qualification, silica spheres – commonly used as fillers in the molding material, was shown to act as a propagation medium that promote the direct interaction of the scribing laser beam and the die surface. Critical to the understanding of the fail mechanism is the deprocessing technique devised to allow layer by layer examination of the metallization and passivation layers in an encapsulated silicon die. The technique also made possible the inspection of the molding compound profile directly on top of the affected die area.

Root-cause analysis of hermetic leak failures is complicated by the difficulty in isolating the leak location. Standard dye penetrant inspection is not consistently successful. The addition of pressure to the dye penetrant, followed by metallographic mounting and preparation, and subsequently followed by vacuum storage, greatly enhances the visibility of the dye and more effectively decorates the leak location.

Two instances of BGA package level failures were identified during in-circuit electrical test. The electrical opens occurred as a result of contamination issues originating at the board supplier. Analytical techniques including optical inspection, SEM/EDS, Raman and FTIR were key in identifying photoresist on the board surface in the first case study and nickel carbonate contamination on the board surface in the second case study. In the first case study, resolution was achieved with a Plasma etch process. In the second case study, CCAs were cleaned with a wet chemical etch process formulated specifically to attack the nickel carbonate.