This paper discusses the application of the RF-LIT technique to a variety of use cases. The technique itself was introduced during last year’s ISTFA 2023 conference. The present work aims to showcase its suitability for the analysis of polyline cracks and packaging related fails such as via opens in RDL as well as cracks in solder joints. Further, a model is constructed explaining why RF-LIT can work and where the frequency dependence comes from.

Over the past decade, the semiconductor industry has increasingly focused on packaging innovations to improve device performance, power efficiency, and reduce manufacturing cost. The recent heterogeneous integration offers an attractive solution in advanced IC packaging because it enables the integration of diverse functional components, such as logic, memory, power modulator, sensor on a single package platform. However, the adoption of the emerging structures, materials and components in advanced packages has challenged the existing fault isolation and analysis techniques. One of the major challenges is the limited accessibility to defects because fault regions are often located deep within devices. Without high-accuracy positional information of a defect, physical cross-sectioning and FIB polishing may alter or destroy the evidence of root causes. A non-destructive microscopic approach is preferred to map defective sites and surrounding structures. However, this method is limited by spatial resolution, especially for analyzing novel submicron interconnects such as fine pitch microbumps, redistribution layers (RDLs), and hybrid bonds. In this paper, we report an AI powered correlative microscopic workflow, where non-destructive X-ray imaging, FIB polishing and high-resolution SEM analyzing techniques are combined to solve the accessibility problem. Because 3D X-ray imaging may take a larger fraction of the time span over the entire workflow, a deep-learning based reconstruction method was applied to accelerate data acquisition. Several next-generation packages, fan-out wafer-level package (FOWLP) and hybrid bonds with sub 10 µm pitch, were used as the test vehicles to demonstrate the workflow performance and efficiency.

In advanced chip package failure investigations, Electro Optical Terahertz Pulse Reflectometry (EOTPR) simulation emerges as a highly effective fault isolation technique. However, traditional manual methods for generating simulation models face significant challenges, including laboriousness, time consumption, and susceptibility to human error. To address these obstacles, we have developed an automation software script in-house. This script autonomously interfaces with the design database, extracting crucial trace information and generating an optimized equivalent trace model. This automated process markedly enhances the efficiency of EOTPR model simulations, streamlining workflow, standardizing procedures, and reducing the potential for human error. The efficacy of integrating the automation script into the workflow of advanced package failure analysis was demonstrated through two case studies. This integration significantly enhanced productivity and enabled successful root-cause investigation of advanced package failures.

The semiconductor industry is no longer driven purely by performance. Miniaturization, increased functionality, low latency and high bandwidth requirements are becoming more important. Furthermore, as Moore’s law scaling becomes more difficult and costly, innovations in packaging technologies through heterogeneous integration are being adopted rapidly to meet these demands. This paper discusses how defects in InFO (Integrated Fan-Out) wafer level multi-die semiconductor packages can be successfully root caused and describes the challenges faced when doing failure analysis of such packages.

In this work we present a new defect localization capability on Wafer Level Chip Scale Packages (WLCSP) with small-scale Cu pillars using advanced 3D X-ray microscopy (XRM). In comparison to conventional microcomputed tomography (Micro-CT or microCT) flat-panel technology, the synchrotron-based optically enhanced 3D X-ray microscopy can detect very small defects with submicron resolutions. Two case studies on actual failures (one from the assembly process and one from reliability testing) will be discussed to demonstrate this powerful defect localization technique. Using the tool has helped speed up the failure analysis (FA) process by locating the defects non-destructively in a matter of hours instead of days or weeks as needed with destructive physical failure analysis.

Government regulations focused on reducing carbon footprint are driving the widespread adoption of cleaner and more energy-efficient electric vehicles (EV/HEV). As electric vehicles continue to be adopted widely, the power electronics market has experienced tremendous growth. To achieve better thermal, electrical, and lifetime reliability, novel processes and advanced materials are frequently assessed, incorporating high temperature/pressure conditions. Given the high safety requirements for vehicles, a reliable power electronics construction is critical. The generic trend in power electronics prompts the evaluation of a robust non-destructive failure analysis technique at the component-level. Scanning acoustic tomography (SAT) stands out as one of the most effective nondestructive tools for conducting failure analysis of the semiconductors. This technique proves valuable for visualizing defect characteristics, including their morphology, location, and size distribution prior to any destructive physical testing. Furthermore, SAT also exhibits a remarkable capability to detect delamination at sub-micron levels. In this paper, one of the most prominent methods of SAT, the “Tomographic Acoustic Micro Imaging” (TAMI) is capable to inspect the sample subsurface layer by layer simultaneously with an excellent penetration of the ultrasonic waves while scanning the material surface. The objective of current work is to detect the defect and localize the defect, nondestructively. The choice of methodologies, such as the structure of device under test, transducer selection and gate setting will be elaborated further in further sections.

3D X-ray microscopy (XRM) is an effective highresolution and non-destructive tool for semiconductor package level failure analysis. One limitation with XRM is the ability to achieve high-resolution 3D images over large fields of view (FOVs) within acceptable scan times. As modern semiconductor packages become more complex, there are increasing demands for 3D X-ray instruments to image encapsulated structures and failures with high productivity and efficiency. With the challenge to precisely localize fault regions, it may require high-resolution imaging with a FOV of tens of millimeters. This may take over hundreds of hours of scans if many high-resolution but small-volume scans are performed and followed with the conventional 3D registration and stitches. In this work, a novel deep learning reconstruction method and workflow to address the issue of achieving highresolution imaging over a large FOV is reported. The AI powered technique and workflow can be used to restore the resolution over the large FOV scan with only a high-resolution and a large FOV scan. Additionally, the 3D registration and stitch workflow are automated to achieve the large FOV images with a recovered resolution comparable to the actual high-resolution scan.

This paper investigates the enhanced inspection of High Bandwidth Memory (HBM) stacks using Scanning Acoustic Microscopy (SAM). As the multi-layer structure is quite complex, sophisticated signal processing methods are employed. To improve detection capabilities and inspection time, the Synthetic Aperture Focusing Technique (SAFT) is utilized. In contrast to previous trials applying SAFT on SAM data, this contribution introduces Near Field SAFT. Reconstruction is also performed for layers between the transducer and its focus, in the near field of the transducer. This approach allows for measurements with common working distances, providing higher frequencies and improved resolution. Systematic evaluations are conducted on various measurement setups and transducers with different center frequencies and focal lengths in order to determine the most optimal measurement setup.

The high temperatures and thermal cycling experienced by integrated circuit packages can induce warpage that in turn can lead to cracks developing at material interfaces that compromise the integrity of electrical traces within the device. In this study, the authors demonstrate how Electro-Optical Terahertz Pulsed Reflectometry (EOTPR) with dynamic temperature control can be used to localize and characterize the resistive faults created by such thermally induced cracks. The EOTPR technique provides quick, reliable, and accurate results, and it allows automatic probing that can be used to generate defect maps for further root cause analysis. The approach demonstrated in this paper shows the significant potential of EOTPR in soft failure characterization and in failure and reliability analysis.

Newly designed products require extensive reliability and stress testing to catch early failures due to defects during fabrication or assembly processes before they can be introduced to the market. Failure analysis plays an important role in verifying these failures and defining the root cause which will drive relevant process resolution and quality improvement. In this paper, the authors demonstrate comprehensive and innovative failure analysis techniques on leakage current localization to prove the defect mechanism of copper migration seen from the internal lead fingers into the die’s substrate on a device with chip-on-lead architecture.