We report on a new non-destructive electrical fault isolation (EFI) technique to localize interconnection failures in through-silicon via (TSV) structures for three-dimensional (3-D) integration. The scanning optical microscopy (SOM) technique is based on light-induced capacitance alteration (LICA) and uses localized photon probing of TSV interconnect capacitance to localize interruptions of electrical connectivity. The technique is applicable to passivated devices and allows rapid, efficient, and non-destructive fault isolation at wafer level. We describe the physics behind signal generation of the technique and demonstrate the TSV photocapacitance effect. We further demonstrate the LICA technique on open failed TSV daisy chain structures and confirm our results with microprobing and voltage contrast measurements in a scanning electron microscope (SEM).

Process challenges and other technology challenges have slowed the implementation of 3D technology into high volume manufacturing well behind the original ITRS expectations. Nevertheless, although full implementation suffered delays, 2.5D through the use of interposer and TSV 3D devices are being already produced, especially in memory devices. These 3D devices (System-in-Package (SiP), wafer-level packaging, Through-Silicon-Vias (TSV), stacked-die, etc.) present major challenges for Failure Analysis (FA) that require novel nondestructive, true 3D Failure Localization techniques. 3D Magnetic field Imaging (MFI), recently introduced, proved to be a natural, useful technique for non-destructively mapping 3D current paths in devices that allowed for submicron vertical resolution. In this paper, we apply this novel technique for 3D localization of an electrically failing complex 2.5D device combining 4Hi-High Bandwidth Memory (HBM) devices and a processor unit on a Si interposer.

To get both the resolution and the field of view needed, 3Di devices are characterized in this paper using phase-contrast X-ray tomography performed in a synchrotron source. The paper shows how the synchrotron-based tomography can be routinely used as a tool for failure analysis, and how some strategies can be applied to make those analyses more time-efficient and automatic without any loss of resolution. It presents and assesses the possibilities offered by a synchrotron radiation facility such as European Synchrotron Radiation Facility for the field of failure analysis in microelectronics. The paper illustrates those possibilities through two main examples, based on two different types of connection of bottom and top tiers in 3D integration, either thermocompression with copper pillars or hybrid bonding using copper pads. Several strategies have been successfully tested for the data acquisition to be faster and to limit the needed human intervention as much as possible.

Within this paper, the authors present an adapted FA flow for state-of-the-art Package Failure Analysis for 20nm technology and below. As a key aspect, three methods (EOTPR, 3D Xray & PFIB) are introduced as the next-gen FA standard methods for emerging package technologies such as TSV, u-pillar bumping and stacked-die devices. By showing different types of daily Package FA requests, the paper compares & discusses important factors such as turn-around-time (TAT), success yield and results quality. In the end, an outlook is given how recent developments on these techniques will help to establish a new standard FA flow.

The growing popularity of 2.5D SSIT (Stacked Silicon Interconnect Technology) & 3D package technology in the IC industry had made it more challenging for manufacturers and packaging assembly sites to perform failure analysis and identifying the root causes of failures. There had been some technical papers written on various failure analysis techniques on 2.5D SSIT and 3D IC packages using a variety of equipment for detecting and localizing failures [1, 2]. This paper explains a non-evasive, non-destructive approach of localizing failures on a 2.5D SSIT package by identifying and recognizing certain waveform patterns that the failing devices exhibit in the scanning acoustic microscope A-Scan and in Time domain reflectometry. There are noticeable waveform patterns that an analyst can recognize and used to determine certain types of failure mechanisms that may be present in the device. Please note that it is very important to use the exact same type of package sample when characterizing and comparing waveform patterns as package variability from vendor to vendor and material contents can certainly affect the results.

It is important to locate a short circuit failure in semiconductor devices, and powerful tools such as lock-in thermography and optical beam induced resistance change are used. However, those tools are inappropriate for investigating the device covered with the impenetrable substance to light, because the covering substance blocks the light from the defect point in the device and also prevents the optical beam from outside of the device. We demonstrate that a subsurface short circuit in a ball grid array device can be located by magnetic field imaging (MFI) and the electromagnetic field reconstruction method (EM-FRM), which makes it possible to calculate a magnetic field in the immediate vicinity of the current that is the source of the field from a measured magnetic field at a distance. Moreover, we visualize the short circuit by three-dimensional X-ray microscopy. MFI is also applied to visualization of a magnetic field created by a current flowing inside a printed circuit board and a light emitting diode package.

Contamination by particles is one of the major causes of failures in integrated circuits. In some cases, particles may absorb moisture leading to electrochemical migration, dendrite growth, and electrical leakage and short failures. This work presents two case studies of particle induced corrosion of copper wire bond that resulted in an electrical failure. In the first case, adjacent pin resistive short failures were found to fail due to corrosion and electrochemical migration at wires that were in contact with calcium chloride particles. Analysis showed that the highly hygroscopic calcium chloride particles absorbed moisture and resulted in corrosion and electrochemical migration of the copper wires. For the second case, an electrical open failure after temperature cycle reliability test was found to be due to an organophosphorus particle being in contact with the wire.

Coating of the Cu bond wire with Pd has been a rather widely accepted method in semiconductor packaging to improve the wire bonding reliability. Based on comparison of a Cu bond wire and a Pd-coated Cu bond wire on AlCu pads that had passed HAST, new insight into the mechanism of the reliability improvement is gained. Our analysis showed the dominant Cu-rich intermetallics (IMC) were Cu3Al2 for the Cu wire, and (CuPdx)Al for the Pd-coated wire. The results have verified the Cu-rich IMC being suppressed by the Pd-coating, which has been extensively reported in literature. Binary phase diagrams of Al, Cu, and Pd indicate that the addition of Pd elevates the melting point and bond strength of (CuPdx)Al compared with CuAl that formed with the bare Cu wire. The improvements are expected to decrease the kinetics of phase transformation toward the more Cu-rich IMC. With the suppression of the Cu-rich IMC, the corrosion resistance of the wire bonding is enhanced and the wire bonding reliability improved. We find that Ni behaves thermodynamically quite similar to Pd in the ternary system of Cu wire bonding, and therefore possesses the potential to improve the corrosion resistance.

Recently a phenomenon has been found that shows different corrosion rates over Al bond pad regardless of different densities of Cl, F components on Al bond pads in different products. According to the results of analysis, the products showed different corrosion rates for different etch conditions of the bond pad opening. For the cause analysis, we conducted a cross-sectional profile comparison between two products with Al bond pads. Based on the result of comparison, we discovered that the side wall profile of the Al bond pad is affected by the etch conditions of the bond pad opening. In some severe cases, it was observed that a small void was formed between the side wall and Al bond pad. Under moist conditions, this void provided moisture between Al bond pad and TiN barrier metal that the electricity contacted. Through this study, we could conclude that the moisture in the void between Al bond pad and TiN barrier metal may create a galvanic corrosive condition.

High speed FIB cross-sectioning of polyimide material was traditionally very difficult because of artifacts created by FIB on the cross section plane. Therefore we propose a simple method, which retains the high speed of the FIB process, but significantly improves the quality of the cross section plane. The method involves a hard mask positioned close to the intended place of the cross section using a precise manipulator. This then enables highly accurate and site-specific FIB cross-sectioning. Cross sections can be made very quickly and with the excellent quality in comparison to standard procedures based on gas-assisted deposition of a protection layer.

Presence of foreign materials (i.e, contamination) can affect the reliability of copper (Cu) bumps when it affects the wettability of the solder and consequently weakens the joint formation of the copper to the substrate. This paper looks at a case of non-wetting of Cu bumps due to silicon contamination induced during assembly processing. In this case study, surface roughness is the main factor being altered when foreign materials contaminate the metal substrate. Sample devices were tested in a resistive open unit and a direct current failing unit, respectively. It was found that the silicon dust present on the substrate in effect "roughens" the surface, thereby decreasing the wettability between the molten solder to the metal substrate. For future studies, it is recommended that the effect of reliability stress activities on the Cu bumps with silicon contaminations be examined to evaluate the risks for possible field failures of this defect.

We have exploited an innovative X-ray tomography system, which is hosted in a Scanning Electron Microscope (SEM). The resolution reached by this equipment is closed to 160nm in 2 dimensions. We imaged Through Silicon Vias (TSV) which have undergone a manufacturing defect and characterized voids within these interconnections.

The trend to higher integration of electronic devices to include more functions into ever-smaller devices, such as mobile phones or tablet computers, drives the development of novel packaging technologies for semiconductor chips. One of the approaches to reduce packaging size and power consumption is to stack multiple silicon chips on top of each other. An alternative approach is the utilization of through-silicon vias (TSV) to connect multiple chips to each other. This paper provides a set of sample preparation and analysis techniques for the comprehensive analysis of TSVs in support of technology development and qualification. The toolset ranges from simple cross-section imaging of cleaved samples to the evaluation of wafer planarity at the end of the TSV process flow and to the more specific analysis of the stress field around TSVs. The results provide valuable insights for designers, integration engineers, and process engineers.

In this paper different sample preparation strategies for fast and efficient failure analysis of 3D devices are reviewed and further explored. It will be shown that a combined workflow using laser ablation and plasma FIB milling provides best flexibility to cover most of the FA use cases. Laser ablation guarantees fast, coarse material removal and the subsequent plasma FIB milling provides fast removal of any damage or imperfections induced by the laser ablation, precise navigation to the region of interest, a high quality surface finish allowing direct SEM imaging and analytics such as EBSD and, if required the preparation of a thin lamella for TEM analysis.

3D tomography of TSVs was performed by combining Xe plasma FIB milling and lift-out techniques. This approach allows analyzing the structure of TSVs in detail using a method faster than the usual 3D tomography by Ga FIB and more precise than X-ray tomography. Both well-filled TSVs and TSVs with voids were analyzed and the results were compared. The analysis procedure was optimized in order to reduce the analysis time and to increase the throughput. The lift-out of the analyzed block of material was performed to obtain 90° angle between TSV and the ion beam axes, which is critical to reduce the curtaining effect and which allowed to increase FIB beam current significantly, reducing the analysis time.

Electro Optical Terahertz Pulse Reflectometry (EOTPR), a terahertz based Time Domain Reflectometry (TDR) technique, has been evaluated on Flip Chip (FC) and 3D packages. The reduced size and complexity of these new generations of advanced IC products necessitate non-destructive techniques with increased fault isolation accuracy. The minimum accuracy achievable with conventional TDR is approximately 1000μm. Here, we show that EOTPR is able to differentiate all of the critical features in a 3D FC package, such as μC4 and Through Silicon Via (TSV), and is capable of producing distance-to-defect accuracy of less than 20μm, a significant improvement over conventional microwave based TDR techniques.

In the past couple years, Space Domain Reflectometry (SDR) has become a mainstream method to locate open defects among the major semiconductor manufacturers. SDR injects a radio frequency (RF) signal into the open trace creating a standing wave with a node at the open location. The magnetic field generated by the standing wave is imaged with a SQUID sensor using RF electronics. In this paper, we show that SDR can be used to non-destructively locate high resistance failures in Micro LeadFrame Packages (MLP).

We developed the non-destructive failure analysis method that is combination of Lock-in thermography (LIT) and high resolution 3D oblique CT. It made possible to complete the total analysis efficiently, because we can distinguish the type of failure by this non-destructive method.

This paper presents an original approach allowing determining the failure mechanism at the origin of onresistance (RDSon) drift on vertical Power N-MOSFETs, dedicated to automotive application. The studied devices failed after Temperature Cycling (TC) qualification stress. The originality of that paper concerns the necessity to use strategic Failure Analysis (FA) approaches to determine the origin of the defect, without any localization possibilities. In that perspective, an original microprobing sub-mohms resistance electrical characterization of the different conductive interfaces was performed in order to determine the failing layer. Then, physical destructive FA techniques (backside SAM, leadframe peel-off and mechanical cross-section) were combined in order to finely characterize the defect. As a result, problems in die attach layer were highlighted, confirming the electrical probing characterization. At last, root cause of this abnormal die attach will be discuss through review of assembly process parameters. These results allowed implementing corrections and improving product stress resistance.

Performance degradation due to fatigue accumulation from the repetitive switching of high load current is critical to understanding robust power MOSFET product design. In this paper, we present a novel high-current-temperature (HCT) characterization system used to investigate real world powercycling failure mechanisms. The effects of electric current Joule heating, non-uniform temperature distribution and performance deterioration of discrete power devices are discussed. Thermal fatigue of solder joints and thick aluminum wire bonding are common weak spots with regard to power-cycling capability. We report performance failure mechanisms and discuss the superposition of contributing factors in defining root cause. Results discuss various package influences as part of a robust power MOSFET development process.