The development of a next generation high-resolution x-ray Computed Tomography (CT) tool and its applications are reported in this paper. Some of the key features are region of interest capability, improved time-to-data, improved usability, and data collection automation capability. We also discuss the key technical challenges that are faced by x-ray CT technology. Critical cases that are hard or not possible to isolate by alternative methods are also discussed. Examples include Controlled Collapse Chip Connection (C4) bump cracking and “invisible” non-wetting analysis, ball grid array (BGA) solder joint cracking, and wirebond microcracking and wirebond shorting, as well as demonstration of progressive testing capability.

The present paper studies several failure mechanisms at both UBM and Cu substrate side for flip-chip die open contact failures in multi-chip-module plastic BGA-LGA packages. A unique failure analysis process flow, starting from non-disturbance inspection of x-ray, substrate and die level C-SAM, bump x-section followed by a bump interface integrity test including under-fill etching and bump pull test and/or substrate etch has been developed. Four different types of failure mechanism in multiple chip module that are associated with open/intermittent contact, ranging from device layout design, UBM forming process defect, to assembly related bump-substrate interface delamination have been identified. The established FA process has been proved to be efficient and accurate with repeatable result. It has facilitated and accelarated new product qualification processes for a line of high power MCM modules.

Some standard characterization techniques (solder ball pull, solder ball shear, etc.) exist for the assessment of solder ball mechanical fracture strength; however, it is not clear if these test methods would also provide characterization of printed circuit board (PCB) pad cratering susceptibility. This paper provides an overview of test methods being investigated by a PCB pad crater industry working group. The scope of this industry working group is two-fold: standardization of PCB pad crater crack characterization and measurement methods and development of a quantitative quality metric for PCB pad cratering. Though the test methods were successful in creating pad craters; there was not enough distinction between the various laminate material types based on the output parameters. Based on the readings from Phase 1 study and available literature, the team is in the process of completing the Phase 2 study which will be reported at a later stage.

This case study shows a typical example of a manufacturing-chain-induced reliability problem. All participants of the chain do their work within specifications, but, looking at the system level, severe reliability problems have been observed. In order to get back into the system-level process window, several corrective actions are possible. In this case, the most promising approach is an improvement of the stitch bond robustness, combined with a clear user specification.

While considerable amount of researches and investigations have been made on lead-free solder joint reliability, limited number of literatures are available on the effect of gold content on lead-free solder joint performance. The challenges of lead-free solder/gold metallization interdiffusion during high temperature application/test are: gold embrittlement, intermetallics growth, void formation, and tin-whisker formation. Tin whiskers causing system failures in earth and space-based applications have been reported. This paper illustrates a few case histories of such challenges. The results confirmed that the synergistic effects of void formation, intermetallic compounds formation due to the thick gold plating, and coefficient of thermal expansion mismatch between organic and ceramic substrates resulted in brittle fracture of the solder joint. The tin whisker formation was attributed to the compressive stress in the tin solder material, which was caused by diffusion of the end-cap metallization, formation of intermetallics, and thermal cycling of the soldered components.

Thick film resistors are widely used in consumer and industrial products such as timers, motor controls and a broad range of high performance electronic equipment. This article provides information on failures due to copper dendrite growth, silver migration, sulfur atmosphere corrosion, variation of temperature, and crack due to molding compound mechanisms. It presents case studies in which a physical analysis plan was developed and executed to investigate these sites of interest on as-manufactured and failed thick film power resistors. The analysis techniques included X-ray inspection, cross-sectioning, decapsulation, and optical and environmental scanning electron microscopy analysis. A table illustrates different failure modes and mechanisms for thick film resistors, and also potential application and manufacturing factors that cause failure mechanisms, which then describe the failure modes. The article is concluded that by preventing the failure of thick film resistors, printed circuit boards can be kept in service for their full lifetime.

Conventional microCTs or 3D x-ray upgrades from existing 2D x-ray systems have two major drawbacks when they are used for failure analysis of advanced packages: Insufficient resolution to image small (1 to 5 microns) materials and the lack of imaging contrast to visualize cracks, whiskers, and defects within low Z materials. This paper discusses some of the failure analysis (FA) case studies of wireless modules using a high resolution micro x-ray CT (XCT). These examples show the value of high resolution XCT as a novel approach to some common package level defects, including some interesting case examples, where failure mechanisms have been uncovered which could not have been done, using conventional means. The non-invasive FA technique for RF modules technique has been shown to dramatically improve the FA engineers' chances of identifying defects over conventional 2D x-rays and avoid the need for physical and tedious cross sectioning of these devices.

This paper reports using Scanning Acoustic Microscopy for solder joint failure analysis and process and design improvements. There are reliability concerns associated with solder voids or non-wetting of the solder to the bond pads which is particularly important for higher electrical power or temperature applications. Defects in solder can also occur and grow during operation and thermal cycling. Sonoscan is an attractive non-destructive test to characterize solder joints and is often used to study the growth of defects during life test simulations. X-ray imaging cannot identify very small defects, particularly non-wetting and delamination because of poor resolution. The instrument used in this study was a CSAM (C-Mode Scanning Acoustic Microscopy) operating in reflection mode at 30-100 MHz. We have identified voids inherent in the solder layer as well as delamination at the package to solder and solder to heat-sink interfaces. C-SAM results confirmed that the delamination was caused by CTE mismatch of the materials as well as the mechanical stresses caused by higher level package integration and module assemblies. Thermal cycling studies have shown that typically the voids do not grow whereas delamination does. These results were used to improve thermal heat-sinking and product reliability by minimizing defects in solder joint by changes in process and mechanical designs.

It has been shown that microscopic Lock-in-Thermography (LiT) can be used for localization of electrical active defects like shorts and resistive opens in integrated circuits. This paper deals with the application of LiT for non-destructive failure analysis of fully packaged single and multi chip devices. In this case inner hot spots generated by the electrical defects typically can not be imaged directly because the mold compound or adhesives above are not IR transparent. Inner hot spots can only be detected by measuring the corresponded temperature field at the device surface. By means of failed and test devices will be shown, that LiT is sensitive enough to measure such temperature fields. In addition to the lateral localization of inner hot spots its depth can also be determined by measuring the phase shift between the electrical excitation and the thermal response at the device surface. Furthermore, the influence of the lock-in-frequency and mold compound thickness to lateral resolution and signal to noise ratio will be discussed. Using real failed single chip and stacked die devices two analysis flows were demonstrated to locate inner defects.

Damage to encapsulated integrated circuits has recently been reported due to Laser marking of the package. A method to assess the risk of such damage is presented. The method is an analytical technique using Thermally Induced Voltage Alteration (XIVA) and Optical Beam Induced Current (OBIC) imaging.

This paper describes the electrical signatures and failure analysis techniques used to identify plastic encapsulated devices that have failed due to silver migration. This migration, which produces resistive leakages between adjacent pins, has been associated with molding compounds that utilize red phosphorous as a flame retardant material. A description of the failure mechanism is also presented.

With the growing complexity of integrated circuits (IC) comes the issue of quality control during the manufacturing process. In order to avoid late realization of design flaws which could be very expensive, the characterization of the mechanical properties of the IC components needs to be carried out in a more efficient and standardized manner. The effects of changes in the manufacturing process and materials used on the functioning and reliability of the final device also need to be addressed. Initial work on accurately determining several key mechanical properties of bonding pads, solder bumps and coatings using a combination of different methods and equipment has been summarized.

In a prequalification effort to evaluate the assembly process for the industrial grade high pin count devices for use in a high reliability application, one device exhibited characteristics that, without corrective actions and/or extensive screening, may lead to intermittent system failures and unacceptable reliability. Five methodologies confirmed this conclusion: (1) low post-decapsulation wire pull results; (2) bond shape analysis showed process variation; (3) Failure Analysis (FA) using state of the art equipment determined the root causes and verified the low wire pull results; (4) temperature cycling parts while monitoring, showed intermittent failures, and (5) parts tested from other vendors using the same techniques passed all limits.

The bump nodule growing in electroplating process could be large enough to induce bump to bump short even if the nodule would be weaken by re-flow process. In this work, the microstructure of PbSn eutectic bump and Au bump nodules was analyzed with FIB, SEM and EDS. In PbSn eutectic bump nodule, void defects can be observed with FIB imaging. In Au bump nodule, radiation-like grain structure around the center of Silicon-contained particle can be observed. Based on those analysis results, voids and particles are the source of bump nodule growth. The reason for bump nodule formation is that particles, voids and cathode morphology defects change the roughness of cathode surface, which induces a higher current density area and accelerate local electrocrystallization. Generally, particles, voids and cathode morphology defects are caused by poor photolithography process, tank corrosion and anode contamination such as passivation membrane. Therefore, three conclusions are proposed in this work: 1) where and when the nodules grow can be identified according to their microstructures; 2) cleaning tank and anode periodically can effectively prevent the bump nodules; 3) Qualified photo resist (PR) coating and PR opening process are essential to prevent bump nodule defects.

An aggressive yield improvement program that was undertaken by the engineering teams has culminated in the works reported in this paper. The power down current (Idd_Pd) was one of the major failure modes recorded for CMOS ICs. In essence, any improvement made on the Idd_Pd test yield will result in substantial gain in terms of cost and production capacity. A taskforce to resolve high fallouts for the Idd_Pd was then formed back in the year 2004. This taskforce comprised of members from various engineering teams, for instance, Manufacturing, IC Design, Materials and Failure Analysis (FA). The length of investigation to resolve the complex high Idd_Pd failures had spanned over a period of a year. The team had devised a comprehensive sets of DOEs (Design of Experiments) which were conducted at various contract manufacturing facilities where the ICs were packaged. Results obtained from these DOEs had conclusively pointed to molded materials as the major factor contributing to high Idd_Pd yield loss. Armed with this vital information, FA had performed an indepth electrical diagnosis as well as physical analysis on the molded materials. The analysis results had confirmed contamination of the molding materials by conductive carbonized resin as the cause of high leakage current in ICs. Likewise, the material supplier had found minute contamination in the resin melt. In essence, Idd_Pds that were measured in the range of tens of microamps to thousands of microamps in ICs could be largely attributed to leakages caused by carbonized resin in the molded materials.

Accelerated corrosion leading to system failure has been observed on printed circuit boards present in industrial environments that contain abnormal levels of reduced sulfur gasses, such as hydrogen sulfide (H2S) and elemental sulfur. The problem is compounded by the fact that elemental sulfur is regulated by OSHA as a nuisance dust, and is allowed in a human working environment at the parts per thousand levels. Anecdotal data shows clearly that elemental sulfur gas present at the parts per million level can cause computer systems to fail within 2 months of use. Newer technologies such as immersion silver plating are especially susceptible to this type of corrosion. With the rapid growth of organically coated copper (OCC) and immersion silver platings, the number of failures due to reduced sulfur gasses in the environment has risen substantially.

Multi-Chip Package (MCP) decapsulation is now becoming a rising problem. Because for traditional decapsulation method, acid can’t dissolve the top silicon die to expose the bottom die surface in MCP. It makes inspecting the bottom die in MCP is difficult. In this paper, a new MCP decapsulation technology combining mechanical polishing with chemical etching is introduced. This new technology can remove the top die quickly without damaging the bottom die using KOH and Tetra-Methyl Ammonium Hydroxide (TMAH). The technology process and relative application are presented. The factors that affect the KOH and TMAH etch rate are studied. The usage difference between the two etchant is discussed.

Previous work on determining the minimal air gap detectable in scanning acoustic microscope (SAM) focused on the gap thickness detectable in an idealized Newton ring sample using a 75 MHz transducer. However, air gaps thinner than 0.130 microns have been detected by SAM. These findings have prompted a return to the question of what is the minimal air gap detectability of SAM. To answer this question, further, Newton Ring experiments using transducers across the SAM frequency range have been performed. This article discusses the processes involved in these experiments and provides the results of SAM from actual packages. The procedure involved in cross-sectioning and scanning electron microscopy (SEM) imaging for correlating samples is also provided. Based on the SAM-cross-sectioning-SEM analysis, a detection of 0.056 - 0.183 micron air gaps was concluded for the delamination areas detected by SAM using a 35 MHz 12 mm transducer.

The semiconductor industry is recognizing an increasing need to define the compatibility of various products joined in package-on-package configuration by solder reflow. Within the scope of the application, this paper discusses: sample preparation; warpage data collection methods; extraction of usable images and numerical data from the measurements; creation of visual warpage patterns for the top and bottom components of stacked package sets; mathematical determination of variation or separation of parts at critical locations during reflow; and finite element analysis of parts and processes to understand and predict reactions to design changes.

Stacked-die packaging was used to make an octal 20-bit analog-to-digital (A/D) converter by stacking two quad A/D converter die in a single 48-lead QFN (quad flat-pack, no leads) package. Reliability testing for product qualification initially failed only (biased) HAST test. Two failure mechanisms were identified. The first mechanism was silver ion migration at sensitive analog inputs due to high conductive die-attach fillets on the bottom die. The second mechanism was ILD delamination and passivation layer cracking due to spacer-attach stress on the surface of the bottom die. Electrical failure analysis was aided by a self test mode designed into the quad A/D converter. Package opening and other standard failure analysis techniques required some modification to accommodate the stacked-die package. This work points to critical stacked-die assembly steps, including conductive die-attach and nonconductive spacer-attach application, where effects of moisture, bias, and thermal stress must all be considered.