In this paper we report on the application field of Dynamic Laser Stimulation (DLS) techniques to Integrated Circuit (IC) analysis. The effects of thermal and photoelectric laser stimulation on ICs are presented. Implementations, practical considerations and applications are presented for techniques based on functional tests like Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). A new methodology, Delay Variation Mapping (DVM), will also be presented and discussed.

Soft Defect Localization (SDL) is an analysis technique where changes in the pass/fail condition of a test are monitored while a laser is scanned across a die.[1,2,3,4] The technique has proven its usefulness for quickly locating failing nodes for functional fails that are temperature, frequency, and/or voltage dependant. The localized heating from the laser can toggle the pass/fail condition as it sweeps over failing nodes with the aforementioned sensitivity. The technique is instrumental in identifying latent defect locations on conditional fails even though they seldom produce light emissions or liquid crystal hot spots. These fails often manifest themselves after reliability stress or at the customer. The technique can also be applied to support design groups with first silicon analysis of timing race conditions and identification of signals that are speed path limiters. The main challenges associated with the technique are in synchronizing the tester with the Laser Scanning Module (LSM) and ensuring the laser can heat the device enough to overcome the pass/fail threshold temperature of the failing node.

Infra-red Thermal Laser Stimulation (TLS) signatures obtained on semiconductor materials can be difficult to interpret and to distinguish from signatures from metallic materials. Investigations presented here consist in the study of TLS signals on unsilicided/silicided polycrystalline and diffused silicon resistors of 0.18µm technology. The influence of each process parameter on the TLS signal has been observed and evaluated from the front and back side of the circuit. This allowed us to quantify the effect of the silicon substrate thickness on TLS signal detection and to determine the ideal silicon thickness for sample preparation. This study also completes our methodology based on the TCR parameter which aims at improving defect localization in the depth (Z) of circuitry. As it will be shown through failure analysis case studies, this methodology increases the physical analysis success rate and reduces the turnaround time.

A new localization method called LIA-SDL is introduced and applied to scan shift problems. The method combines local thermal stimulation technique with lock-in technique applied to periodical test pattern. The localization capability on soft defects is shown in comparison with SDL. Same localization results are obtained. LIA-SDL technique requires no special LSM (Laser Scan Microscope) facilities and is quite easy to handle. Limits and prospects of this new methodology are shown at several analysis examples.

In this paper we present the advanced optical testing of an array fabricated in IBM’s 65 nm SOI CMOS technology, using the Picosecond Imaging Circuit Analysis (PICA) [1-11] tool equipped with the Superconducting Single-Photon Detector (SSPD) [12,13]. Based on the results of the optical analysis we were able to confirm a time collision problem in the readout circuit of the array. In the following sections we will also discuss the use of an innovative optical packaging for testing chips requiring wire-bonding, along with record low voltage optical measurements, down to 0.7 V.

Time-Resolved Emission (TRE) is a popular technique for non-invasive acquisition of time-domain waveforms from active nodes through the backside of an integrated circuit. [1] State-of-the art TRE systems offer high bandwidths (> 5 GHz), excellent spatial resolution (0.25um), and complete visibility of all nodes on the chip. TRE waveforms are typically used for detecting incorrect signal levels, race conditions, and/or timing faults with resolution of a few ps. However, extracting the exact voltage behavior from a TRE waveform is usually difficult because dynamic photon emission is a highly nonlinear process. This has limited the perceived utility of TRE in diagnosing analog circuits. In this paper, we demonstrate extraction of voltage waveforms in passing and failing conditions from a small-swing, differential logic circuit. The voltage waveforms obtained were crucial in corroborating a theory for some failures inside an 0.18um ASIC.

This paper describes the analysis of a Phase-Locked Loop (PLL) internal phase detection circuit built in IBM’s 0.13 µm Silicon On Insulator (SOI) CMOS technology by using the Picosecond Imaging Circuit Analysis (PICA) [1,2] tool equipped with the high quantum efficiency Superconducting Single-Photon Detector (SSPD) [3,4]. Signals corresponding to the internal nodes of the PLL are for the first time measured and compared to circuit simulations in order to characterize the behavior of the different components of the circuit.

This paper describes case histories of 0.13 um bulk CMOS technology analyses using Time Resolved Light Emission (TRLEM). Using this technique, scan chain, timing, and logic failures are shown to be quickly and decisively identified thereby meeting the need for rapid feedback on 1st silicon failures and process excursions.

The capabilities of photon emission microscopy with CCD and MCT camera systems for the 90 nm CMOS technology node were investigated. This was done with a dedicated test circuit with selectable shorts with resistance between 0 to 40 kΩ. Our investigations showed that conventional PEM with CCD systems is not possible anymore due to the reduction in photon emission intensity in the visible range. However, photon emission can be enhanced by using elevated supply voltages. For these overdrive conditions PEM with a CCD system is still feasible. We furthermore show that PEM is in principle capable of determining the state of a circuit and that PEM in combination with defect simulations can determine defect characteristics. In this manner, for example, the resistance of a short can be estimated by localising the PMOST emission spot.

Given the ever increasing complexity of conducting failure analysis on today's latest generation manufacturing processes, the authors have investigated and implemented OBIRCH techniques into process development failure analysis practices. They describe their applications of OBIRCH to 120, 90, and 65 nm samples and their methods for interpreting the results. The OBIRCH technique has the ability to address faults within most structure types and quickly give information on a number of failing sites. It has proven itself as a necessary tool for failure analysis at advanced technology nodes, where fault characterization is getting difficult due to extremely small critical dimensions. The results obtained using the OBIRCH tool have been excellent on 120nm and initial 90nm results. The authors have not yet analyzed enough 65nm samples to form any type of conclusion regarding the tools ability at this technology node.

In thermal microscopy, temperature error arises whenever a constant emissivity value is assumed for different materials. In this paper, we propose a new approach to eliminate these undesirable effects resulting from the ambiguous surface emissivity of materials. This method enables the compensated (true) temperature distribution of a device under test to be obtained from the measured temperature image. A transfer function that relates the measured and true temperature is formed to estimate the actual temperature distribution of a biased device to an accuracy of approximately 0.3-0.7K.

In this paper we discuss the use of Emission Microscopy (EMMI) to examine the events leading to latchup for various Input/Output (I/O) pins of a test chip in order to study the factors that impact latchup sensitivity of VLSI chips. The goal of our study is to identify and characterize the structures that are most prone to latchup in test chips, thus providing countermeasures to be used to improve the overall latchup resistance of commercial chips. As it has been shown in literature [1-3], EMMI can be used to localize areas that are latching up. Here we focus our attention on electrostatic discharge (ESD) into I/O pins, which may lead to latchup inside I/O circuits or in their proximity.

Thermal laser signal injection microscopy (T-LSIM) (aka TIVA and OBIRCH) has shown considerable promise in stateof- the-art digital integrated circuits. The technique has been utilized to locate shorts, leakage currents, problem vias, and timing issues in these devices. However, little has been published on the utility of this technique for analog and mixed signal devices. In this paper we demonstrate the application of T-LSIM on two different analog devices with defects that conventional FA technology and fault isolation techniques were unable to locate. Analog devices produce several unique challenges to the basic T-LSIM technique as typically utilized in the digital regime. Extensions of the basic T-LSIM technique were utilized to locate the failures, which produced unexpected results. The T-LSIM technique has proved essential in the quick identification and localization of failure sites. The T-LSIM technique provides the failure analyst with the analytical power not previously available on conventional fault isolation tools such as emission microscopy and liquid crystal.

Internal node timing probing of silicon integrated circuits (ICs) has been a mainstay of the microelectronics industry since very early in its history. In recent years, however, due in part to the increase in the number of interconnection layers and continued proliferation of packaging techniques exposing only the silicon substrate, conventional probing technologies such as e-beam and mechanical probing have become cumbersome or impractical. In an effort to continue transistor-level probing, backside optical probing technologies have been developed and adopted [1]. Chronologically, such techniques include picosecond image circuit analysis (PICA)[2], laser voltage probing (LVP)[3], and dynamic or time-resolved emission (TRE)[4]. In typical examples of backside probing the device under test (DUT) relies on device stimulation from automatic test equipment (ATE) or equivalent bench top setup. This generally requires a specially designed DUT card designed to accommodate a low-profile socket and lid. The DUT card, which is significantly smaller than the tester motherboard, is designed to fit within the chamber opening of the probe system in order to interact with the optical column. Tester stimulation of packaged parts, however, does not address the need to probe the DUT in-situ and in the intended application, such as a PC board. It is often desirable to probe the DUT under conditions typical of the final product or running standardized application based tests. We present here this application and have addressed some of the challenges associated with PC card based optical probing and show successfully performed time-resolved emission on a second-generation advanced graphics processor in a standard graphics card.

The use of time resolved photon emission (TRPE) to compare internal measurements with simulations can dramatically reduce the time required for IC analysis. During debug, this technique makes it possible to probe only transistors of interest. Two limitations must be overcome: precise location of transistor photon emission areas and distinction between photons emitted by closely spaced transistors. Otherwise results may be seriously biased. Introducing CAD auto-channeling for TRPE makes it possible to generate virtual layers where emissions are expected. As a result, transistor TRPE areas can be automatically located and emission from nearby transistors is taken into account, thus significantly reducing the duration of IC analysis.

In this paper we examine the use of the Superconducting Single-Photon Detector (SSPD) [1] for extracting electrical waveforms on an IBM microprocessor fabricated in a 0.13µm technology with 1.2V nominal supply voltage. Although the detector used in our experiments is prototype version of the one discussed in [1] demonstrating lower performance, we will show that it provides a significant reduction in acquisition time for the collection of optical waveforms, thus maintaining the usability of the PICA technique for present and future low voltage technologies.