Abstract A functional fail of a DRAM is analyzed by using an analog output of the device as an input signal of a microscope. Local heating by an IR laser changes the pass/fail behavior and thus the analog output of the DRAM. Although the observed spots do not belong to the physical defect, they give a starting point for further electrical analysis leading to the root cause of the failure. The paper will present a case study on a state-of-the art DRAM device failing with a timing problem. Especially the test aspects as well as the setup for the temperature dependent localization will be described. Finally an interpretation of the results will be proposed.

Abstract Embedded cache size has dramatically increased with the advent of Intel Hyper-Threading and Multi-Core Technology, making many of the existing cache test validation method less and less practical, if not obsolete. As a result, the effort to sustain and improve array test quality, which is ever so critical to achieve DPM goals, is becoming a formidable challenge. In this paper, we present a test content validation procedure through novel application of Laser Assisted Device Alteration (LADA), i.e. soft fault injection in state elements, which had proven itself in Itanium® 2 array test quality improvement. While the procedure was originally targeting cache test content, the underlying concept has been successfully deployed to expedite scan test content and fault isolation tool validation.

Abstract In this paper, we demonstrate two applications of time-resolved emission (TRE): measurement of dynamic, local power-supply (Vdd) variations, and synchronous timing jitter induced by Vdd variations. The first technique measures the height of many peaks within a TRE waveform; differences in peak height are correlated with inter- pulse differences in Vdd. The second technique measures the timing of all of the peaks and extracts the inter-pulse timing variations. The measurement was automated and was performed on long (multiple-μs) acquisition windows containing hundreds of emission peaks. Our work advances the state of the art by using the peak heights and positions to extract this information, and by performing the measurements in an automated fashion.

Abstract Optical beam induced resistance change (OBIRCH) is one popular technique for isolating electrical shorts in process development test structures for 130nm and 110nm device technologies. However, OBIRCH inspection on 90nm technology is not always successful: since the OBIRCH signals of samples are very weak, or even comparable to noise. To overcome this, two alternative and complementary methods for isolating the failure have been developed. The first method is to calculate the coarse position of the defect directly from electrical resistance measurements. The second method is to enhance the OBIRCH signal using FIB circuit modification within the test structure. These methods can help locate defect at this structure by using electrical analysis only or enhancing the OBIRCH signal. The first method is an easy and quick method for short failure isolation, while the second can exactly locate the position of failure if the first method does not reveal a surface defect.